EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

AS7C33128PFS16B-166TQC

Description
Standard SRAM, 128KX16, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
Categorystorage    storage   
File Size444KB,14 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric View All

AS7C33128PFS16B-166TQC Overview

Standard SRAM, 128KX16, 8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33128PFS16B-166TQC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time8 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX16
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
Base Number Matches1
Shanghai Hangxin ACM32F070 development board + serial port
Continuing from the last review, the link is as follows: https://bbs.eeworld.com.cn/thread-1221177-1-1.html These are skipped for new construction projects. Prepare the serial port assistant:The inter...
meiyao Domestic Chip Exchange
Welcome to Analog Circuit Moderator
Welcome to Analog Circuit Moderator...
yanmei Analog electronics
Motion Estimation Algorithm Design and FPGA Implementation.pdf
Motion Estimation Algorithm Design and FPGA Implementation.pdf...
zxopenljx EE_FPGA Learning Park
Purgatory Legend-Generate War.pdf
Purgatory Legend-Generate War...
雷北城 FPGA/CPLD
What Ceddie said - the nerve center of RFID technology - middleware
RFID is one of the top ten strategic technologies that enterprises are recommended to consider introducing in 2005, and middleware can be called the core of RFID operation because it can accelerate th...
JasonYoo RF/Wirelessly
In FPGA design, timing is everything
When your FPGA design fails to meet timing, the reason may not be obvious. The solution depends not only on using FPGA implementation tools to optimize the design to meet timing requirements, but also...
fish001 Microcontroller MCU

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号