IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
LOW VOLTAGE PLL
CLOCK DRIVER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014
IDT5V9351
FEATURES:
•
•
•
•
•
•
•
•
•
Fully integrated PLL
Output frequency up to 200MHz
2.5V and 3.3V Compatible
Compatible with PowerPC™, Intel, and high performance RISC
microprocessors
Output frequency configurable
Cycle-to-cycle jitter max. 22ps RMS
Compatible with MPC9351
Available in TQFP package
Use replacement part 87951AYI-147LF
DESCRIPTION:
The IDT5V9351 is a high performance, zero delay, low skew, phase-lock
loop (PLL) clock driver. It has four banks of configurable outputs. The
IDT5V9351 uses a differential PECL reference input and an external feedback
input. These features allow the IDT5V9351 to be used as a zero delay, low
skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK,
a CMOS clock driver input.
If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing
so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will
be divided down to four output banks.
When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will
be clocked in both phase and frequency to FBIN. PECL clock is activated by
setting REF_SEL to low.
FUNCTIONAL BLOCK DIAGRAM
(pullup)
0
REF
t
CLK
REF_
SEL
FBIN
(pulldown)
1
1
0
2
4
8
1
0
D
Q
Q
A
PECL_CLK
PECL_CLK
(pulldown)
(pulldown)
PLL
FB
200 - 400MHz
0
D
1
PLL_En
(pullup)
Q
Q
B
Q
C
0
0
f
SELA
f
SELB
f
SELC
f
SELD
(pulldown)
1
(pulldown)
Q
D
0
(pulldown)
Q
D
1
(pulldown)
0
D
1
Q
D
3
Q
Q
D
2
D
Q
Q
C
1
Q
D
4
OE
(pulldown)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2013 Integrated Device Technology, Inc.
MAY 2013
DSC-5972/18
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
REF_SEL
PLL_EN
TCLK
GND
GND
V
CC
Q
A
Q
B
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
I
V
O
I
IN
24
23
22
21
20
19
18
17
Description
Supply Voltage
Input Voltage
DC Output Voltage
Input Current
DC Output Current
Storage Temperature
Max.
–0.3 to +4.6
–0.3 to V
CC
+0.3
–0.3 to V
CC
+0.3
±20
±50
–55 to +150
Unit
V
V
V
mA
mA
°C
32
VCCA
FBIN
f
SELA
f
SELB
f
SELC
f
SELD
GND
PECL_CLK
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
Q
C0
V
CC
Q
C1
GND
Q
D0
V
CC
Q
D1
GND
I
O
T
STG
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
10
11
12
13
14
15
16
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation
Capacitance
Min.
Typ.
4
10
Max.
Unit
pF
pF
V
CC
PECL_CLK
Q
D4
V
CC
GND
Q
D3
Q
D2
OE
—
—
—
—
TQFP
TOP VIEW
GENERAL SPECIFICATIONS
Symbol
V
TT
HBM
LU
Description
Output Termination Voltage
ESD (Human Body Model)
Latch-Up Immunity
2000
200
Min.
Typ.
V
CC
/2
Max.
Unit
V
V
mA
LOGIC DIAGRAM
(1,2)
R
F
V
CC
C
F
10nF
V
CCA
V
CC
33...100nF
NOTES:
1. IDT5V9351 requires an external RC filter for the analog power supply pin V
CCA
.
2. For V
CC
= 2.5V, R
F
= 9-10Ω, C
F
= 22μF.
For V
CC
= 3.3V, R
F
= 5-15Ω, C
F
= 22μF.
2
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
PECL-CLK
PECL-CLK
TCLK
FBIN
REF_SEL
f
SEL(D:A)
OE
Q
A
Q
B
Q
C (1:0)
Q
D (4:0)
V
CCA
V
CC
GND
PLL_EN
30
2
32
3, 4, 5, 6
10
28
26
22, 24
12, 14, 16,
18, 20
1
11, 15, 19,
23, 27
7, 13, 17, 21,
25, 29
31
I
PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled.
Ground
Negative power supply
PWR
PWR
Positive power supply for PLL
Positive power supply for I/O and core
I
I
I
I
I
O
O
O
O
Single-ended reference clock signal or test clock
Feedback signal input
Reference clock input
Frequency control pin
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock output
Bank D clock output
No.
8, 9
Type
I
Description
Differential clock reference, LOW voltage positive ECL input
FUNCTIONALITY
Control
REF_SEL
PLL_EN
OE
FSELA
FSELB
FSELC
FSELD
Default
0
1
0
0
0
0
0
0
Selects PECL_CLK as reference clock
Test mode with PLL Disabled
Outputs enabled
Q
A
= V
CO
÷
2
Q
B
= V
CO
÷
4
Q
C
= V
CO
÷
4
Q
D
= V
CO
÷
4
1
Selects TCLK as reference clock
PLL Enabled
Outputs disabled
Q
A
= V
CO
÷
4
Q
B
= V
CO
÷
8
Q
C
= V
CO
÷
8
Q
D
= V
CO
÷
8
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
3
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
INPUTS
f
SELA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
f
SELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
f
SELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
f
SELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q
A
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
CLK
CLK
2 * CLK
2 * CLK
CLK
CLK
2 * CLK
2 * CLK
OUTPUTS
Q
B
CLK
CLK
2 * CLK
2 * CLK
CLK
÷
2
CLK
÷
2
CLK
CLK
CLK
CLK
2 * CLK
2 * CLK
CLK
÷
2
CLK
÷
2
CLK
CLK
Q
C
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Q
D
CLK
CLK
÷
2
2 * CLK
CLK
CLK
CLK
÷
2
2 * CLK
CLK
CLK
CLK
÷
2
2 * CLK
CLK
CLK
CLK
÷
2
2 * CLK
CLK
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
DC ELECTRICAL CHARACTERISTICS
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 5%
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
Z
OUT
I
IN
I
CC
I
CCPLL
Parameter
Input HIGH Voltage
Input LOW Voltage
Peak-to-Peak Input Voltage
Common Mode
(1)
Output HIGH Voltage
(2)
Output LOW Voltage
(2)
Output Impedance
Input Leakage Current
Maximum Quiescent Supply Current
Maximum PLL Supply Current
Test Conditions
LVCMOS Inputs
LVCMOS Inputs
PECL_CLK
PECL_CLK
I
OH
= -24mA
I
OL
= 24mA
I
OL
= 12mA
Min.
2
—
250
1
2.4
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
14 - 17
—
—
3
Max
V
CC
+ 0.3
0.8
—
V
CC
- 0.6
—
0.55
0.3
—
±150
1
5
Unit
V
V
mV
V
V
V
Ω
μA
mA
mA
All V
CC
Pins
V
CCA
Only
NOTES:
1. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range and the input swing lies within the V
PP
(DC) specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to V
CC
/2) transmission lines on the incident edge.
4
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PLL INPUT REFERENCE CHARACTERISTICS
V
CC
= 3.3V ± 5%, T
A
= -40°C to +85°C
Symbol
t
R
, t
F
f
REF
Parameter
TCLK Input Rise/Fall Levels, 0.8V to 2V
÷
2 feedback
Reference Input Frequency
(1)
Static Test Mode
Reference Input Duty Cycle
Min.
—
100
50
25
0
25
Max
1
200
100
50
300
75
Unit
ns
MHz
÷
4 feedback
÷
8 feedback
f
REF
DC
%
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.
AC ELECTRICAL CHARACTERISTICS
(1)
T
A
= -40°C to +85°C, V
CC
= 3.3V ± 5%
Symbol
t
R
, t
F
V
PP
V
CMR
t
PW
t
SK
(
O
)
f
VCO
f
MAX
t
PD
t
PLZ
, t
PHZ
t
PZL
, t
PZH
B
W
t
J
t
JIT
(
PER
)
t
JIT
(φ)
t
LOCK
Parameter
Output Rise/Fall Time
Peak-to-Peak Input Voltage
Common Mode Range
Output Duty Cycle
Output to Output Skew
PLL VCO Lock Range
Maximum Output Frequency
Propagation Delay (Static Phase Offset)
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
Cycle-to-Cycle Jitter
÷
4 feedback
(Single Output Frequency Configuration)
Period Jitter
÷
4 feedback
(Single Output Frequency Configuration)
I/O Phase Jitter
Maximum PLL Lock Time
(2)
Conditions
0.55V to 2.4V
LVPECL
LVPECL
100-200 MHz
50-100 MHz
25-50 MHz
Min.
0.1
500
1.2
45
47.5
48.75
—
200
100
50
25
-50
25
—
—
Typ.
—
—
—
50
50
50
—
—
—
—
—
—
—
—
—
9 - 20
3 - 9.5
1.2 - 2.1
10
8
4 - 17
—
Max
1
1000
V
CC
- 0.9
55
52.5
51.75
150
400
200
100
50
150
325
10
10
—
—
—
22
15
—
1
Unit
ns
mV
V
%
ps
MHz
MHz
ps
ns
ns
MHz
ps
ps
ps
ms
÷
2 output
÷
4 output
÷
8 output
TCLK to FBIN
PECL_CLK to FBIN
÷
2 feedback
÷
4 feedback
÷
8 feedback
RMS Value
RMS Value
RMS Value
-3db point of
PLL transfer
characteristic
—
—
—
—
—
—
—
NOTES:
1. AC Characteristics apply for parallel output termination of 50Ω to V
TT
.
2. V
CMR
(
AC
) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input swing lies within V
PP
(
AC
)
specifications.
5
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