DUAL IO-LINK MASTER TRANSCEIVER WITH UARTs
PRODUCTION DATA - NOV 27, 2013
E981.12
Features
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
2-port IO-Link Master
Integrated UART-Interface for each port
Output drivers with typical 1 Ω
Supporting external PMOS switches for
IO-Link supply (L+) with current limitation
Wake-up generation support
Supply voltage range
V
VDDH
: 8V – 32V / V
VDD
: 3.15V - 3.45V
Over-current & short-circuit protection at output
stages with configurable thresholds
Digital inputs configurable for IO-LINK or
IEC 61131-2 compatible interface
SPI for communication, configuration,
and diagnosis
Under voltage monitor for all supplies
Over temperature protection
General Description
This device comes with two independently operating
IO-Link MASTER PHYs which make it a perfect fit for
2/4/8/16-port Master applications. Especially for multi-
port applications the integrated UARTs offer you high
flexibility regarding scalability of Master ports and the
choice of the μC used for the application. As the E981.12
allows the support of external MOSFETs for sensor sup-
ply, it enables cost-effective and power dissipation op-
timized system concepts.
The dual IO-Link Master is also available as SIP at RENE-
SAS with embedded microcontroller for protocol han-
dling.
Ordering Information
Ordering No.:
E98112A39B
Ambient Temp. Range
-40°C to +105°C
Package
QFN44L7
Applications
ÿ
IO-Link Master application in modular SPS
ÿ
Gateway applications
Typical Application Circuit
VIN
VDD
VDDH
External
Voltage
Regulator
GND
INTN
Supply Monitor
Overtemperature,
Overvoltage
Protection
L1
L2
e.g. RSHUNT
=100mΩ
Current
Amplifier
NCS
SCLK
MOSI
MISO
RXD1
RXD2
SPI
System
Control
UARTs
OC [1:2]
SENSE_L1
SENSE_L2
DR_L1
DR_L2
e.g. RON
=100mΩ
L+1
L+2
Gate Driver
RXD [1:2]
External
µC
CQ_IN1
CQ_IN2
L+ [1:2]
TXEN1
TXD1
TXEN2
TXD2
ILIM [1:2]
WAKE [1:2]
TXD [1:2]
TXEN [1:2]
CTRL
CQ_OUT1
CQ_OUT2
CQ1
CQ2
E981.12
GND
PGND1
PGND2
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0069E.02
1/34
DUAL IO-LINK MASTER TRANSCEIVER WITH UARTs
PRODUCTION DATA - NOV 27, 2013
VIN
E981.12
Functional Diagram
VDD
VDDH
External
Voltage
Regulator
GND
INTN
Supply Monitor
Overtemperature,
Overvoltage
Protection
L1
L2
e.g. RSHUNT
=100mΩ
Current
Amplifier
NCS
SCLK
MOSI
MISO
RXD1
RXD2
SPI
System
Control
UARTs
OC [1:2]
SENSE_L1
SENSE_L2
DR_L1
DR_L2
e.g. RON
=100mΩ
L+1
L+2
Gate Driver
RXD [1:2]
External
µC
CQ_IN1
CQ_IN2
L+ [1:2]
TXEN1
TXD1
TXEN2
TXD2
ILIM [1:2]
WAKE [1:2]
TXD [1:2]
TXEN [1:2]
CTRL
CQ_OUT1
CQ_OUT2
CQ1
CQ2
E981.12
GND
PGND1
PGND2
Pin Configuration
Top View
Bottom Side
XTAL_OUT
CLK_OUT
XTAL_IN
Pin 1
VDDH
n.c.
i.c.
GND
VDD
n.c.
n.c.
35
44
43 42
41
40
39 38
37 36
SENSE_L1
DR_L1
L1
CQ_OUT1
CQ_IN1
PGND1
PGND2
CQ_IN2
CQ_OUT2
n.c.
34
33
1
2
3
4
5
6
7
8
9
EP
n.c.
TXEN1
RXD1
TXD1
INTN
GND
VDD
RXD2
TXD2
TXEN2
n.c.
32
31
30
29
E981.12
12 13
14
15
16 17
18
19
20 21
22
28
27
26
25
24
23
L2
10
DR_L2
11
GND
SCSN
SENSE_L2
SCLK
MISO
i.c.
MOSI
GND
VDD
n.c.
n.c.
Not to scale !
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0069E.02
2/34
DUAL IO-LINK MASTER TRANSCEIVER WITH UARTs
PRODUCTION DATA - NOV 27, 2013
E981.12
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Name
SENSE_L1
DR_L1
L1
CQ_OUT1
CQ_IN1
PGND1
PGND 2
CQ_IN2
CQ_OUT2
L2
DR_L2
SENSE_L2
GND
i.c.
SCSN
SCLK
MOSI
MISO
GND
VDD
n.c.
n.c.
n.c.
TXEN2
TXD2
RXD2
VDD
GND
INTN
TXD1
RXD1
TXEN1
n.c.
n.c.
n.c.
n.c.
CLK_OUT
VDD
GND
D_O
S
S
D_I
D_I
D_O
S
S
D_O
D_I
D_O
D_I
D_I
D_I
D_I
D_O
S
S
Type
1)
HV_A_I
HV_A_O
HV_S
HV_A_O
HV_A_I
HV_S
HV_S
HV_A_I
HV_A_O
HV_S
HV_A_O
HV_A_I
S
Description
Supply current sense input channel 1
PMOS Gate control output channel 1
Transceiver supply input channel 1
Transmitter output channel 1
Receiver / general purpose input channel 1
Power ground channel 1
Power ground channel 2
Receiver / general purpose input channel 2
Transmitter output channel 2
Transceiver supply input channel 2
PMOS Gate control output channel 2
Supply current sense input channel 2
System ground
Internally connected. For factory use only. Connect to GND in application
SPI chip select input
SPI serial clock input
SPI master output slave input (data input)
SPI master input slave output (data output)
System ground
3.3V voltage supply
not connected
not connected
not connected
Transmitter enable channel 2
Transmitter input channel 2
Receiver output channel 2
3.3V voltage supply
System ground
Interrupt output (low active)
Transmitter input channel 1
Receiver output channel 1
Transmitter enable channel 1
not connected
not connected
not connected
not connected
Clock output port
3.3V voltage supply
System ground
1) A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0069E.02
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DUAL IO-LINK MASTER TRANSCEIVER WITH UARTs
PRODUCTION DATA - NOV 27, 2013
Pin
40
41
42
43
44
-
Name
XTAL_IN
i.c.
n.c.
VDDH
EP
S
S
Type
1)
D_I
Description
External quartz
External quartz
E981.12
XTAL_OUT D_O
Internally connected. For factory use only. To be left open in application
not connected
High-voltage supply input
Exposed Die Pad
1) A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress rat-
ings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages
with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.
PGND1, PGND2, GND1 and the package exposed pad must be soldered to the same GND potential.
Description
DC voltage at pin VDDH
Transient voltage at pin VDDH
(ESD, burst, surge)
DC input voltage at pins CQ_INx
DC input voltage at pins CQ_OUTx
DC voltage at pins Lx, SENSE_Lx, DR_Lx
Synchronous transient voltage at pins
CQ_OUTx and Lx
Continuous DC voltage at VDD
Voltage range for digital interface pins
RXDx, TXDx, TXENx, INTN, MISO, MOSI,
SCLK, SCSN
Maximum IO current at each pin, if not
specified otherwise
Junction temperature
Storage temperature
ESD protection at pins CQ_OUTx and
CQ_INx
ESD protection at pin VDDH
ESD protection at pins CQ_OUTx and
CQ_INx
ESD protection at pin VDDH
ESD protection at all other pins
Condition
continuous
t < 500μs
continuous
continuous
continuous
t < 500μs
continuous
continuous
Symbol
V
SUP
V
SUP,trans
V
CQ_IN_dc
V
CQ_OUT_dc
V
L_CTRL
V
L_CTRL,trans
V
VDD
V
IF
I
IO_LUP
Min
-0.3
-0.3
-5
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-40
6
6
6
6
2
Max
40
60
40
V
DDH
+0.3
V+0.3
60
3.6
V
DD
+0.3
10
150
150
Unit
V
V
V
V
V
V
V
V
mA
°C
°C
kV
kV
kV
kV
kV
continuous
AEC-Q100-002
R=1.5kΩ, C=100pF
chip level test
AEC-Q100-002
R=1.5kΩ, C=100pF
chip level test
IEC 61000-4-2
R=330Ω, C=150pF
IEC 61000-4-2
R=330Ω, C=150pF
AEC-Q100-002
R=1.5kΩ, C=100pF
chip level test
T
J
T
STG
V
CQ_ESD_HBM
V
VDDH_ESD_
HBM
V
CQ_ESD
V
VDDH_ESD
V
pin_ESD_HBM
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0069E.02
4/34
DUAL IO-LINK MASTER TRANSCEIVER WITH UARTs
PRODUCTION DATA - NOV 27, 2013
E981.12
2 Recommended Operating Conditions
Parameters are guaranteed within the range of recommended operating conditions unless otherwise specified.
All voltages are referred to ground (0V).
Currents flowing into the circuit have positive values.
The first electrical potential connected to the IC must be GND.
Description
Supply voltage at pin VDDH
Supply voltage at pin VDDH for
IOLINK communication
Supply voltage at pin VDD
Operating ambient temperature
range
Condition
SIO Mode
IO_Link Mode
Symbol
V
VDDH
V
VDDH
V
VDD
T
OP
Min
8
18
3.15
-40
Typ
24
24
3.3
Max
32
32
3.45
+105
Unit
V
V
V
°C
3 Thermal Characteristics
Description
Thermal resistance junction to
case
Condition
QFN44L7
1)
Symbol
R
TH_JC_7_ABS
R
TH_JAH_7_ABS
Min
Typ
5
25
Max
Unit
K/W
K/W
Thermal resistance junction to am- QFN44L7
1)
bient, high conductivity
1) Values are based on multilayer PCB according to JEDEC JESD-51-5.
4 Electrical Characteristics
(V
VDDH
= +8V to +32V for SIO mode, V
VDD
=3.15V to 3.45V, T
AMB
= -40°C to +105°C, unless otherwise noted. Typical
values are at V
VDDH
= +24V, V
VDD
= +3.3V and T
AMB
= +25°C. Positive currents flow into the device pins.)
Description
Power Supplies
Supply voltage at pin VDDH for
SIO mode
Supply voltage at pin VDDH for
IOLINK communication
Supply voltage at pin VDD
Supply current at pin VDDH
Supply current at pin VDD
Supply Monitors
Under voltage threshold VDDH, L1,
L2 to switch-off the transmitters
or the external P-FETs
Under voltage monitor threshold
at L1 and L2
Debounce time for under voltage
detection at VDDH, L1 and L2
VDD undervoltage threshold
Hysteresis of VDDUV threshold
UV
OFF
UV
IOLINK
t
deb_UV
V
DDUV
V
DDUVhyst
6.5
16
50
2.7
0.1
7
17
7.5
18
250
3
V
V
μs
V
V
SIO mode
V
supSIO
V
supIOLINK
V
DD
I
DDH
I
DD
8
18
3.15
24
24
3.3
1.0
3.5
32
32
3.45
2.0
5.5
V
V
V
mA
mA
Condition
Symbol
Min
Typ
Max
Unit
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0069E.02
5/34
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