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28F016XS
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
SYNCHRONOUS FLASH MEMORY
n
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n
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Backwards-Compatible with 28F008SA
Command-Set
2 µA Typical Deep Power-Down
1 mA Typical Active I
CC
Current in
Static Mode
16 Separately-Erasable/Lockable
128-Kbyte Blocks
1 Million Erase Cycles per Block
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Effective Zero Wait-State Performance
up to 33 MHz
Synchronous Pipelined Reads
SmartVoltage Technology
User-Selectable 3.3V or 5V V
CC
User-Selectable 5V or 12V V
PP
0.33 MB/sec Write Transfer Rate
Configurable x8 or x16 Operation
56-Lead TSOP and SSOP Type I
Package
Intel’s 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining very high read performance with the intrinsic
nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of
shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for
improved system performance. The innovative capabilities of the 28F016XS enable the design of direct-
execute code and mass storage data/file flash memory systems.
The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution
available today. Its synchronous pipelined read interface, flexible V
CC
and V
PP
voltages, extended cycling,
fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a
highly flexible memory component suitable for resident flash component arrays on the system board or
SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface
with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read
performance up to 33 MHz. The 28F016XS’s dual read voltage allows the same component to operate at
either 3.3V or 5.0V V
CC
. Programming voltage at 5V V
PP
minimizes external circuitry in minimal-chip, space
critical designs, while the 12.0V V
PP
option maximizes program/erase performance. Its high read performance
combined with flexible block locking enable both storage and execution of operating systems/application
software and fast access to large data tables. The 28F016XS is manufactured on Intel’s 0.6 µm ETOX IV
process technology.
November 1996
Order Number: 290532-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016XS may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
CONTENTS
PAGE
1.0 INTRODUCTION ............................................ 7
1.1 Product Overview ........................................ 7
2.0 DEVICE PINOUT........................................... 10
2.1 Lead Descriptions ...................................... 12
3.0 MEMORY MAPS ........................................... 14
3.1 Extended Status Register Memory Map..... 15
4.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS............. 16
4.1 Bus Operations for Word-Wide Mode
(BYTE# = V
IH
)........................................... 16
4.2 Bus Operations for Byte-Wide Mode
(BYTE# = V
IL
) ........................................... 17
4.3 28F008SA—Compatible Mode Command
Bus Definitions.......................................... 18
4.4 28F016XS—Enhanced Command Bus
Definitions ................................................. 19
4.5 Compatible Status Register ....................... 20
4.6 Global Status Register ............................... 21
4.7 Block Status Register ................................ 22
4.8 Device Configuration Code ........................ 23
4.9 SFI Configuration Table ............................. 23
28F016XS FLASH MEMORY
PAGE
5.0 ELECTRICAL SPECIFICATIONS ................. 24
5.1 Absolute Maximum Ratings ....................... 24
5.2 Capacitance............................................... 24
5.3 Transient Input/Output Reference
Waveforms............................................... 26
5.4 DC Characteristics (V
CC
= 3.3V) ................ 27
5.5 DC Characteristics (V
CC
= 5.0V) ................ 30
5.6 Timing Nomenclature ................................. 33
5.7 AC Characteristics—Read Only
Operations ................................................ 34
5.8 AC Characteristics for WE#—Controlled
Write Operations ....................................... 40
5.9 AC Characteristics for CE X#—Controlled
Write Operations ....................................... 44
5.10 Power-Up and Reset Timings .................. 48
5.11 Erase and Program Performance............. 49
6.0 MECHANICAL SPECIFICATIONS ................ 51
APPENDIX A: Device Nomenclature and
Ordering Information .................................. 53
APPENDIX B: Additional Information............... 54
3
28F016XS FLASH MEMORY
E
REVISION HISTORY
Description
Number
-001
-002
Original Version
Removed support of the following features:
•
All page buffer operations (read, write, programming, Upload Device Information)
•
Command queuing
•
Software Sleep and Abort
•
Erase all Unlocked Blocks and Two-Byte Write
•
RY/BY# Configuration as part of the Device Configuration command
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased I
PPR
(V
PP
Read Current) for V
PP
> V
CC
to 200 µA at V
CC
= 3.3V/5.0V.
Changed V
CC
= 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected t
PHCH
(RP# High to CLK) to be a “Min” specification at V
CC
= 3.3V/5.0V.
Corrected the graphical representation of t
WHCH
and t
EHCH
in Figures 15 and 16.
Increased Typical “Byte/Word Program Times” (t
WHRH1A
/t
WHRH1B
) for V
PP
= 5.0V (Sec.
5.13): t
WHRH1A
from 16.5 µs to 29.0 µs and t
WHRH1B
from 24.0 µs to 35.0 µs at V
CC
=
3.3V
t
WHRH1A
from 11.0 µs to 20.0 µs and t
WHRH1B
from 16.0 µs to 25.0 µs at V
CC
= 5.0V.
Increased Typical “Block Program Times” (t
WHRH2
/ t
WHRH3
) for V
PP
= 5.0V (Section 5.13):
t
WHRH2
from 2.2 sec to 3.8 sec and t
WHRH3
from 1.6 sec to 2.4 sec at V
CC
= 3.3V
t
WHRH2
from 1.6 sec to 2.8 sec and t
WHRH3
from 1.2 sec to 1.7 sec at V
CC
= 5.0V.
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values
at V
CC
=3.3/5.0V and V
PP
=5.0/12.0V (Section 5.13).
Minor cosmetic changes throughout document.
-003
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and
Lead Descriptions (Section 2.1)
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin
Added 3/5# pin to Test Conditions of I
CCS
Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)
Removed Note 7 of Section 5.7
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode
support ONLY)
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t
5VPH
and t
3VPH
specifications; Added t
PLYL
, t
PLYH
, t
YLPH
, and t
YHPH
specifications
Added SSOP pinout (Figure 2) and Mechanical Specifications
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Minor cosmetic changes throughout document.
4
E
Number
-004
28F016XS FLASH MEMORY
REVISION HISTORY
(Continued)
Description
Require all V
CC
Tolerences to be within 5% of Operational Voltage
I
PPES
Is Pushed to 200 µA from 50 Max
I
CCD
Is Pushed to 10 µA from 5 Max
Updated t
AVAV
at 3.3V
Updated t
ELEH
at 3.3V and 5.0V
5
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