DATASHEET
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
Description
The ICS9DB403 is compatible with the Intel DB400v2 Differential
Buffer Specification. This buffer provides 4 PCI-Express Gen2 clocks.
The ICS9DB403 is driven by a differential output pair from a
CK410B+, CK505 or CK509B main clock generator.
ICS9DB403D
Features/Benefits
•
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Output Features
•
•
•
•
•
4 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Key Specifications
•
•
•
•
•
•
•
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
28-pin SSOP/TSSOP pacakge
Available in RoHS compliant packaging
Supports Commercial (0 to +70°C) and Industrial (-40 to
+85°C) temperature ranges
Functional Block Diagram
2
4
-OE(6, 1)
OE(6,5,2,1)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
U
X
STOP
LOGIC
DIF(6,5,2,1)
PD
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDT
®
Four Output Differential Buffer for PCIe and Gen 1 and Gen 2
ICS9DB403D
REV R 11/1/12
1
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Configuration
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE_INV = 0
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
DIF_STOP#
PD#
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE_INV = 1
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
HIGH_BW#
DIF_STOP
PD
ICS9DB403D
(same as ICS9DB104)
28-pin SSOP & TSSOP
Polarity Inversion Pin List Table
OE_INV
Pins
8
15
16
21
0
OE_1
PD#
DIF_STOP#
OE_6
1
OE1#
PD
DIF_STOP
OE6#
Power Groups
Pin Number
VDD
GND
1
4
5,11,18, 24
4
N/A
27
28
27
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
(same as ICS9DB401)
ICS9DB403D
REV R 11/1/12
2
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Decription When OE_INV = 0
PIN #
PIN NAME
PIN TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD#
DIF_STOP#
HIGH_BW#
VDD
DIF_5#
DIF_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
DESCRIPTION
3.3V power for differential input clock (receiver). This VDD should be treated
as an analog power rail and filtered appropriately.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 =disable outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal osc. (if any) are
stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 =disable outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference for the differential current-mode output
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require different
values. See data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV R 11/1/12
3
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Decription When OE_INV = 1
PIN #
PIN NAME
PIN TYPE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD
DIF_STOP
HIGH_BW#
VDD
DIF_5#
DIF_5
OE6#
DIF_6#
DIF_6
VDD
OE_INV
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
DESCRIPTION
3.3V power for differential input clock (receiver). This VDD should be
treated as an analog power rail and filtered appropriately.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active high input pin used to power down the device.
The internal clocks are disabled and the VCO is stopped.
Active High input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference for the differential current-mode
output pairs. It requires a fixed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
impedances require different values. See data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV R 11/1/12
4
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Absolute Max
Symbol
VDDA/R
VDD
V
IL
V
IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Commerical Operating Range
Industrial Operating Range
Case Temperature
Input ESD protection
human body model
Min
Max
4.6
4.6
V
DD
+0.5V
-65
0
-40
150
70
85
115
Units
V
V
V
V
C
°C
°C
°C
V
°
GND-0.5
2000
Electrical Characteristics - Clock Input Parameters
T
A
= Tambient for the desired operating range, Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage -
DIF_IN
Input Low Voltage -
DIF_IN
Input Common Mode
Voltage - DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to
Cycle
1
SYMBOL
V
IHDIF
V
ILDIF
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
Peak to Peak value
(single-ended measurement)
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
600
V
SS
- 300
300
300
0.4
-5
45
0
TYP
800
0
MAX
1150
300
1000
1450
8
5
55
125
UNITS NOTES
mV
mV
mV
mV
V/ns
uA
%
ps
1
1
1
1
1,2
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing min centered around differential zero
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV R 11/1/12
5