A1460A-1TQG176I datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> A1460A-1TQG176I

A1460A-1TQG176I: Descriptionfpga - field programmable gate array 6K system gates; CategoryProgrammable logic devices Programmable logic; File Size546KB，98 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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A1460A-1TQG176I Overview

fpga - field programmable gate array 6K system gates

A1460A-1TQG176I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	1.40 MM HEIGHT, TQFP-176
Reach Compliance Code	compliant
Other features	MAX 151 I/OS
maximum clock frequency	116.8 MHz
Combined latency of CLB-Max	2.6 ns
JESD-30 code	S-PQFP-G176
JESD-609 code	e3
length	24 mm
Humidity sensitivity level	3
Configurable number of logic blocks	848
Equivalent number of gates	6000
Number of entries	168
Number of logical units	848
Output times	168
Number of terminals	176
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	848 CLBS, 6000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP176,1.0SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	24 mm

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v3.0

HiRel FPGAs

Fe a t ur es

• Low-Power 0.8µ CMOS Technology

32 0 0D X Fe a t ur es

• Highly Predictable Performance with 100% Automatic

Placement and Routing

• Device Sizes from 1,200 to 20,000 Gates

• Up to 6 Fast, Low-Skew Clock Networks

• Up to 202 User-Programmable I/O Pins

•

More Than 500 Macro Functions

Up to 1,276 Dedicated Flip-Flops

I/O Drive to 10 mA

Devices Available to DSCC SMD

CQFP and CPGA Packaging

Nonvolatile, User Programmable

Logic Fully Tested Prior to Shipment

100% Military Temperature Tested (–55°C to +125°C)

QML Certified Devices

• 100 MHz System Logic Integration

• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable

Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Low-Power 0.6µ CMOS Technology

12 0 0X L Fe at ure s

• Pin for Pin Compatible with ACT 2

• System Performance to 50 MHz over Military Temperature

• Low-Power 0.6µ CMOS Technology

A CT 2 Fe at ure s

• Proven Reliability Data Available

• Successful Military/Avionics Supplier for Over 10 Years

A CT 3 Fe at ure s

• Best-Value, High-Capacity FPGA Family

• System Performance to 40 MHz over Military Temperature

• Low-Power 1.0µ CMOS Technology

A CT 1 Fe at ure s

• Highest-Performance, Highest-Capacity FPGA Family

• System Performance to 60 MHz over Military Temperature

• Lowest-Cost FPGA Family

• System Performance to 20 MHz over Military Temperature

• Low-Power 1.0µ CMOS Technology

Pr od uc t F am i l y P r o f i l e

(more devices on

page 2)

Family

Device

Capacity

System Gates

Logic Gates

SRAM Bits

Logic Modules

S-Modules

C-Modules

Decode

Flip-Flops (Maximum)

User I/Os (Maximum)

Performance

System Speed (maximum)

Packages (by Pin Count)

CPGA

CQFP

3200DX

A32100DX

15,000

10,000

2,048

1,362

700

662

738

152

55 MHz

A32200DX

30,000

20,000

2,560

2,414

1,230

1,184

1,276

202

55 MHz

A1425A

3,750

2,500

310

160

150

435

100

60 MHz

133

132

ACT 3

A1460A

9,000

6,000

848

432

416

976

168

60 MHz

207

196

A14100A

15,000

10,000

1,377

697

680

1,493

228

60 MHz

257

256

1200XL

A1280XL

12,000

8,000

1,232

624

608

998

140

50 MHz

176

172

208, 256

J an u a r y 2 0 0 0

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