64Mb: x32
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
MT48LC2M32B2 - 512K x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/sdramds
PIN ASSIGNMENT (TOP VIEW)
86-PIN TSOP
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic Package - OCPL
1
86-pin TSOP (400 mil)
• Timing (Cycle Time)
5ns (200 MHz)
5.5ns (183 MHz)
6ns (166 MHz)
7ns (143 MHz)
• Operating Temperature Range
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
NOTE:
1. Off-center parting line
2. Available on -7
Part Number Example:
MARKING
2M32B2
TG
-5
-55
-6
-7
None
IT
2
MT48LC2M32B2TG-7
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-7
CLOCK
ACCESS TIME
FREQUENCY
CL = 3*
200 MHz
183 MHz
166 MHz
143 MHz
4.5ns
5ns
5.5ns
5.5ns
SETUP
TIME
1.5ns
1.5ns
1.5ns
2ns
HOLD
TIME
1ns
1ns
1ns
1ns
Note:
The # symbol indicates signal is active LOW.
2 Meg x 32
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
*CL = CAS (READ) latency
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
64Mb: x32
SDRAM
64Mb (x32) SDRAM PART NUMBER
PART NUMBER
MT48LC2M32B2TG
ARCHITECTURE
2 Meg x 32
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 67,108,864-bits. It
is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank, A0-A10 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 64Mb SDRAM uses an internal pipelined archi-
tecture to achieve high-speed operation. This archi-
tecture is compatible with the 2n rule of prefetch archi-
tectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while ac-
cessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed,
random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
64Mb: x32
SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 2 Meg x 32 .................
Pin Descriptions .....................................................
Functional Description
.........................................
Initialization ......................................................
Register Definition ............................................
Mode Register ...............................................
Burst Length ............................................
Burst Type ...............................................
CAS Latency ............................................
Operating Mode ......................................
Write Burst Mode ....................................
Commands
............................................................
Truth Table 1 (Commands and DQM Operation)
............
Command Inhibit .............................................
No Operation (NOP) ..........................................
Load Mode Register ...........................................
Active ................................................................
Read ................................................................
Write ................................................................
Precharge ...........................................................
Auto Precharge ..................................................
Burst Terminate .................................................
Auto Refresh ......................................................
Self Refresh ........................................................
Operation
...............................................................
Bank/Row Activation ........................................
Reads ................................................................
Writes ................................................................
Precharge ...........................................................
Power-Down ......................................................
Clock Suspend ..................................................
Burst Read/Single Write ....................................
4
5
6
6
6
6
6
7
8
8
8
9
9
10
10
10
10
10
10
10
10
11
11
11
12
12
13
19
21
21
22
22
Concurrent Auto Precharge ..............................
Write with Auto Precharge ...............................
Truth Table 2 (CKE)
................................................
Truth Table 3 (Current State, Same Bank)
.....................
Truth Table 4 (Current State, Different Bank)
.................
Absolute Maximum Ratings ..................................
DC Electrical Characteristics
and Operating Conditions ......................................
I
DD
Specifications and Conditions .........................
Capacitance ............................................................
23
24
25
26
28
30
30
30
32
AC Electrical Characteristics
(Timing Table) .... 32
AC Electrical Characteristics ................................... 34
Timing Waveforms
Initialize and Load Mode Register ....................
Power-Down Mode ..........................................
Clock Suspend Mode ........................................
Auto Refresh Mode ...........................................
Self Refresh Mode .............................................
Reads
Read – Single Read .......................................
Read – Without Auto Precharge .................
Read – With Auto Precharge .......................
Alternating Bank Read Accesses ..................
Read – Full-Page Burst .................................
Read – DQM Operation ..............................
Writes
Write – Single Write .....................................
Write – Without Auto Precharge ................
Write – With Auto Precharge ......................
Alternating Bank Write Accesses .................
Write – Full-Page Burst ................................
Write – DQM Operation .............................
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
64Mb: x32
SDRAM
FUNCTIONAL BLOCK DIAGRAM
2 Meg x 32 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
BANK0
COMMAND
DECODE
MODE REGISTER
REFRESH 11
COUNTER
11
11
ROW-
ADDRESS
MUX
11
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
2048
BANK0
MEMORY
ARRAY
(2,048 x 256 x 32)
4
4
DQM0-
DQM3
SENSE AMPLIFIERS
32
8192
DATA
OUTPUT
REGISTER
2
A0-A10,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
13
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
32
256
(x32)
DATA
INPUT
REGISTER
32
DQ0-
DQ31
2
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
8
8
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
64Mb: x32
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
68
SYMBOL
CLK
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self refresh
modes, providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal
for write accesses and an output enable signal for read accesses. Input data
is masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ0-
DQ7; DQM1 corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23;
and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same
state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A10 are sampled during the ACTIVE command (row-
address A0-A10) and READ/WRITE command (column-address A0-A7 with A10
defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
67
CKE
Input
20
CS#
Input
17, 18, 19
16, 71, 28, 59
WE#, CAS#,
RAS#
DQM0-
DQM3
Input
Input
22, 23
25-27, 60-66, 24
BA0, BA1
A0-A10
Input
Input
2, 4, 5, 7, 8, 10, 11, 13,
74, 76, 77, 79, 80, 82, 83,
85, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51,
53, 54, 56
14, 21, 30, 57, 69, 70, 73
3, 9, 35, 41, 49, 55, 75, 81
6, 12, 32, 38, 46, 52, 78, 84
1, 15, 29, 43
44, 58, 72, 86
DQ0-DQ31
Input/ Data I/Os: Data bus.
Output
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
–
Supply
Supply
Supply
Supply
No Connect: These pins should be left unconnected. Pin 70 is reserved
for SSTL reference voltage supply.
DQ Power Supply: Isolated on the die for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: +3.3V ±0.3V. (See note 27 on page 35.)
Ground.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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