CXL1511M
CCD Delay Line for PAL
Description
The CXL1511M is an IC developed for use in
conjunction with Y/C signal processing ICs for PAL.
This CCD delay line provides the comb filter output
for eliminating the chrominance signal cross talk and
1H delay output for luminance signals.
Features
•
•
•
•
Single power supply (5V)
Built-in triplex progression PLL circuit
Comb filter characteristics selectable
Delay time for 1H delay output selectable
24 pin SOP (Plastic)
•
Built-in peripheral circuits
•
Positive phase signal input, positive phase signal
output
Functions
•
Comb filter output
•
1H delay output for luminance signal
•
Clock driver
•
Autobias circuit
•
Input clamp circuit (for luminance signals)
•
Center bias circuit (for chrominance signals)
•
Sample-and-hold circuit
•
Triplex progression PLL circuit
•
Luminance signal delay time/comb filter
characteristics selection circuit
•
Clock buffer output circuit
Absolute Maximum Ratings
(Ta = 25°C)
•
Supply voltage
V
DD
+6
V
•
Operating temperature
Topr –10 to +60 °C
•
Storage temperature
Tstg –55 to +150 °C
•
Allowable power dissipation P
D
500 mW
Recommended Operating Voltage
(Ta = 25°C)
V
DD
5V ± 5%
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95224-ST
CXL1511M
Recommended Clock Conditions
(Ta = 25°C)
•
Input clock amplitude
V
CLK
0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.)
•
Clock frequency
f
CLK
4.433619MHz
•
Input clock waveform
sine wave
Input Signal Amplitude
Vsig
350mVp-p (Typ.), 575mVp-p (Max.)
Block Diagram and Pin Configuration
(Top View)
PCOUT
C-OUT
VCOIN
CONT
AB-C
AB-P
(NC)
(NC)
(NC)
Vss
24
23
22
21
20
19
18
17
16
15
14
13
PLL
fsc buffer
Selector
Timing
D
Output
circuit (S/H)
Autobias
circuit (C)
1H/2H + D
Autobias
circuit (Y)
Driver
φ1
Driver
φ2
Bias circuit
Bias circuit
Clamp circuit
1H
Output
circuit (S/H)
1
2
3
4
5
6
7
8
9
10
11
12
(NC)
(NC)
V
DD
C-IN1
(NC)
(NC)
Y-IN
Vss
Y-OUT
C-IN2
–2–
(NC)
CLK
Vss
fsc
CXL1511M
Description of Functions
The CXL1511M enables the chrominance comb filter characteristics and luminance signal delay time to be
selected in the control input state.
CONT
L
H
Mode (typical example)
PAL/GBI
4.43NTSC
Chrominance comb filter
chracteristics
2H (1702.5bit)
1H (844.5bit)
Luminance signal delay time
(number of CCD bits)
1H (848.5bit)
1H (842.5bit)
CONT Input Level
L/H
L
H
Min.
—
2.0
Typ.
0
5.0
Max.
0.5
6.0
Unit
V
• fsc Output Pin
The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor
is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a
2.2kΩ pull-down resistor when the fsc output is to be used.
<When in use>
<When not in use>
fsc
fsc
V
DD
2.2k
–4–
CXL1511M
Electrical Characteristics
(Ta = 25°C, V
DD
= 5V, f
CLK
= 4.433619MHz, V
CLK
= 500mVp-p sine wave)
See electrical Characteristics Measurement Circuit
Item
Supply
current
Symbol
IDD1
IDD2
Measurement
condition
1
—
b
b
SW condition
2
b
b
3
b
b
4
a
a
5
a
b
6
7
8
Min.
Typ.
Max.
Unit
NOTE
a — —
a — —
35
50
mA
1
Chrominance Signal Characteristics
(No signals input to Y-IN)
Item
Symbol
Measurement
condition
1
a
(See Note 2)
a
a
a
a
(See Note 4)
a
a
(See Note 5)
50% white
video signal
(See Note 7)
a
a
a
b
b
a
SW condition
2
a
a
a
a
a
a
a
a
a
a
b
b
b
3
b
b
b
b
b
b
b
b
b
b
b
b
4
a
a
a
a
a
a
a
a
a
a
a
a
5
6
7
b
b
b
b
b
b
b
b
d
d
b
b
a
—
260
—
ns
8
52
56
dB
6
–40
–25
dB
5
–0.3
–2
Min.
Typ.
Max.
Unit
NOTE
Low
GLC1
frequency
GLC2
gain
Frequency
response
Linearity
FC1
FC2
LIC1
LIC2
— a
— a
— a
— a
— a
— a
— a
— a
— a
— a
— a
— a
0
2
dB
2
(See Note 3)
–2.7
–1.7
0
dB
3
0
0.3
dB
4
Comb
CCD1
depth min.
CCD2
gain
SNC1
SN ratio
Coupling
level
Delay
time
SNC2
CPC1
CPC2
DC
10
50
mVrms
7
(See Note 8)
b — — a
–5–
京公网安备 11010802033920号
EEWORLD
