CXK581000ATM/AYM/AM/AP
Description
The CXK581000ATM/AYM/AM/AP is a high speed
CMOS static RAM organized as 131072-words by
8 bits.
A polysilicon TFT cell technology realized extremely low
stand- by current and higher data retention stability.
Special feature are low power consumption, high
speed and broad package line-up.
The CXK581000ATM/AYM/AM/AP ia a suitable
RAM for portable equipment with battery back up.
Features
•
Fast access time:
CXK581000ATM/AYM/AM/AP
-55LL/55SL
(Access time)
55ns (Max.)
CXK581000AM
32 pin SOP (Plastic)
-55LL/70LL/10LL
-55SL/70SL/10SL
131072-word
×
8-bit High Speed CMOS Static RAM
CXK581000ATM
32 pin TSOP (Plastic)
CXK581000AYM
32 pin TSOP (Plastic)
CXK581000AP
32 pin DIP (Plastic)
•
•
•
•
•
•
•
•
-70LL/70SL
70ns (Max.)
-10LL/10SL
100ns (Max.)
Low standby current:
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL
20µA (Max.)
-55SL/70SL/10SL
12µA (Max.)
Low data retention current
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL
12µA (Max.)
-55SL/70SL/10SL
4µA (Max.)
Single +5V supply: +5V ±10%
Low voltage data retention: 2.0V (Min.)
Broad package line-up
CXK581000ATM/AYM
8mm
×
20mm 32 pin TSOP package
CXK581000AM
525mil 32 pin SOP package
CXK581000AP
600mil 32 pin DIP package
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
V
CC
Buffer
Row
Decoder
Memory
Matrix
1024
×
1024
GND
A6
A5
A4
A3
A2
A1
A0
Buffer
I/O Gate
Column
Decoder
OE
Functions
131072-word
×
8-bit static RAM
Structure
Silicon gate CMOS IC
Buffer
WE
I/O Buffer
CE1
CE2
I/O 1
I/O 8
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92756D53-PP
CXK581000ATM/AYM/AM/AP
Pin Configuration (Top View)
A11
A9
A8
A13
WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
Pin Description
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
Symbol
A0 to A16
CE1, CE2
WE
OE
Vcc
GND
NC
Description
Address input
Chip enable 1, 2 input
Write enable input
Output enable input
Power supply
Ground
No connection
I/O1 to I/O8 Data input output
CXK581000ATM
(Standard Pinout)
26
25
24
23
22
21
20
19
18
17
A4
A5
A6
A7
A12
A14
A16
NC
V
CC
A15
CE2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CXK581000AYM
(Mirror Image Pinout)
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
GND
CXK581000AM
CXK581000AP
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Input and output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature
Symbol
V
CC
V
IN
V
I/O
P
D
Topr
Tstg
Tsolder
CXK581000AP
CXK581000ATM/AYM/AM
(Ta = 25°C, GND = 0V)
Rating
–0.5 to +7.0
–0.5
∗
to V
CC
+0.5
–0.5
∗
to V
CC
+0.5
CXK581000AP
CXK581000ATM/AYM/AM
1.0
0.7
0 to +70
–55 to +150
260 • 10
235 • 10
W
°C
°C • s
Unit
V
∗
V
IN
,V
I/O
= –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1
H
×
L
L
L
CE2
×
L
H
H
H
OE
×
×
H
L
×
WE
×
×
H
H
L
Mode
Not selected
Not selected
Output disable
Read
Write
I/O pin
High Z
High Z
High Z
Data out
Data in
V
CC
Current
I
SB1
, I
SB2
I
SB1
, I
SB2
I
CC1
, I
CC2
, I
CC3
I
CC1
, I
CC2
, I
CC3
I
CC1
, I
CC2
, I
CC3
×:
"H" or "L"
DC Recommended Operating Conditions
Item
Supply voltage
Input high voltage
Input low voltage
Symbol
V
CC
V
IH
V
IL
Min.
4.5
2.2
–0.3
∗
(Ta = 0 to +70°C, GND = 0V)
Typ.
5.0
—
—
Max.
5.5
V
CC
+0.3
0.8
Unit
V
∗
V
IL
= –3.0V Min. for pulse width less than 50ns.
–2–
CXK581000ATM/AYM/AM/AP
Electrical Characteristics
• DC Characteristics
Item
Input leakage current
Output leakage current
Operating power
supply current
Symbol
I
LI
I
LO
Test conditions
V
IN
= GND to V
CC
(V
CC
= 5V ±10%, GND = 0V, Ta = 0 to = +70°C)
Min.
–1
–1
Typ.
∗
1
—
—
Max.
1
1
µA
Unit
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
or WE = V
IL
, V
I/O
= GND to V
CC
CE1 = V
IL
, CE2 = V
IH
V
IN
= V
IH
or V
IL
I
OUT
= 0mA
Min. cycle
Duty = 100%
I
OUT
= 0mA
Cycle time 1µs
duty = 100%
I
OUT
= 0mA
CE1
≤
0.2V
CE2
≥
V
CC
– 0.2V
V
IL
≤
0.2V
V
IH
≥
V
CC
– 0.2V
0 to +70°C
CE2
≤
0.2V
LL
∗
2
0 to +40°C
+25°C
0 to +70°C
SL
∗
3
0 to +40°C
+25°C
55LL/55SL
70LL/70SL
10LL/10SL
I
CC1
—
—
—
—
7
45
40
35
15
90
70
60
mA
I
CC2
Average operating
current
I
CC3
—
10
20
—
—
—
—
—
—
—
2.4
—
—
—
0.7
—
—
0.3
0.6
—
—
20
4
2
12
2.4
1
3
—
V
0.4
mA
µA
Standby current
I
SB1
or
{
CE2
≥
V
CE1
≥
V
CC
– 0.2V
CC
– 0.2V
I
SB2
Output high
voltage
Output low
voltage
V
OH
V
OL
CE1 = V
IH
or CE2 = V
IL
I
OH
= –1.0mA
I
OL
= 2.1mA
∗
1 V
CC
= 5V, Ta = 25°C
∗
2 For -55LL/70LL/10LL
∗
3 For -55SL/70SL/10SL
–3–
CXK581000ATM/AYM/AM/AP
I/O Capacitance
Item
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Test conditions
V
IN
= 0V
V
I/O
= 0V
Min.
—
—
(Ta = 25°C, f = 1MHz)
Typ.
—
—
Max.
7
8
Unit
pF
Note)
This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions
Item
Input pulse high level
Input pulse low level
input rise time
input fall time
Input and output reference level
-55LL/55SL
Output load conditions
-70LL/70SL
-10LL/10SL
∗
C
L
includes scope and jig capacitances.
(V
CC
= 5V±10%, Ta = 0 to +70°C)
Conditions
V
IH
= 2.2V
V
IL
= 0.8V
TTL
• Test circuit
t
r = 5ns
t
f = 5ns
1.5V
C
L
∗
= 30pF, 1TTL
C
L
∗
= 100pF, 1TTL
C
L
–4–
CXK581000ATM/AYM/AM/AP
• Read cycle
(WE = "H")
-55LL/55SL
Item
Read cycle time
Symbol
Min.
55
—
—
—
—
15
10
5
—
—
Max.
—
55
55
55
30
—
—
—
25
25
-70LL/70SL
Min.
70
—
—
—
—
15
10
5
—
—
Max.
—
70
70
70
40
—
—
—
25
25
-10LL/10SL
Min.
100
—
—
—
—
15
10
5
—
—
Max.
—
100
100
100
50
—
—
—
35
35
ns
Unit
t
RC
t
AA
Address access time
t
CO1
Chip enable access time (CE1)
t
CO2
Chip enable access time (CE2)
t
OE
Output enable to output valid
t
OH
Output hold from address change
t
LZ1
,
t
LZ2
Chip enable to output in low Z (CE1, CE2)
t
OLZ
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2)
t
HZ1
,
t
HZ2
∗
t
OHZ
∗
Output disable to output in high Z (OE)
referred to as output voltage levels.
∗
t
HZ1
,
t
HZ2
and
t
OHZ
are defined as the time required for outputs to turn to high impedance state and are not
• Write cycle
-55LL/55SL
Item
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
Symbol
Min.
55
50
50
25
0
40
0
0
0
10
—
Max.
—
—
—
—
—
—
—
—
—
—
25
-70LL/70SL
Min.
70
60
60
30
0
50
0
0
0
10
—
Max.
—
—
—
—
—
—
—
—
—
—
25
-10LL/10SL
Min.
100
70
70
40
0
70
0
0
0
10
—
Max.
—
—
—
—
—
—
—
—
—
—
30
ns
Unit
t
WC
t
AW
t
CW
t
DW
t
DH
t
WP
t
AS
t
WR
t
WR1
t
OW
t
WHZ
∗
∗
t
WHZ
is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
–5–
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