T4240
QorIQ Integrated Multicore
Communications Processor
Datasheet DS1146
FEATURES
•
12 e6500 cores built on Power Architecture
®
technology and
arranged as clusters of four e6500 cores sharing a 2 MB L2
cache
•
1.5 MB CoreNet platform cache (CPC)
•
Hierarchical interconnect fabric
– CoreNet fabric supporting coherent and non‐coherent
transactions with prioritization and bandwidth allocation
amongst CoreNet end‐points
– 1.6 Tbps coherent read bandwidth
•
Three 64‐bit DDR3 SDRAM memory controllers
– DDR3 and DDR3L with ECC and interleaving support
•
Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Packet parsing, classification, and distribution (Frame
Manager 1.1)
– Queue management for scheduling, packet sequencing,
and congestion management (Queue Manager 1.1)
– Hardware buffer management for buffer allocation and
de‐allocation (Buffer Manager 1.1)
– Cryptography Acceleration (SEC 5.0)
– RegEx Pattern Matching Acceleration (PME 2.0)
– Decompression/Compression Acceleration (DCE 1.0)
– DPAA chip‐to‐chip interconnect via RapidIO
Message Manager (RMan 1.0)
•
32 SerDes lanes at up to 10 GHz
•
Ethernet interfaces
– Up to four 10 Gbps Ethernet MACs
– Up to sixteen 1 Gbps Ethernet MACs
– Combinations of 1 Gbps and 10 Gbps Ethernet MACs
– IEEE Std 1588
™
support
•
High‐speed peripheral interfaces
– Four PCI Express 2.0/3.0 controllers running at up to 8
Gbps with one controllers supporting end‐point,
single‐root I/O virtualization (SR‐IOV)
– Two Serial RapidIO 2.0 controllers running at up to 5
Gbps
– Interlaken look‐aside interface for TCAM connection
•
Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high‐speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller (SD/MMC/
eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2‐pin UARTs or two 4‐pin DUARTs
– Integrated flash controller supporting NAND and NOR
flash
•
Three 8‐channel DMA engines
•
1932 FC‐PBGA package, 45 mm × 45 mm, 1mm pitch
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, France
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
Holding Company: Teledyne e2v Semiconductors SAS
Teledyne e2v Semiconductors SAS 2018
1146D–HIREL–10/18
T4240
1.
OVERVIEW
The T4240 QorIQ integrated multicore communications processor combines 12 dual‐threaded cores
built on Power Architecture
®
technology with high‐performance data path acceleration and network
and peripheral bus interfaces required for networking, telecom/ datacom, wireless infrastructure, and
military/aerospace applications.
This chip can be used for combined control, data path, and application layer processing in routers,
switches, gateways, and general‐purpose embedded computing systems. Its high level of integration
offers significant performance benefits compared to multiple discrete devices, while also simplifying
board design.
This figure shows the block diagram of the chip.
Figure 1‐1.
Block diagram
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
512 KB
Plat Cache
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
2 MB Banked L2
512 KB
Plat Cache
MPIC
PreBoot Loader
Security Monitor
Internal BootROM
Power mgmt
SD/MMC
eSPI
4 x UART
4x I
2
C
IFC
2 x USB2.0 w/PHY
Clocks/Reset
GPIO
CCSR
DCE
CoreNet
TM
Coherency Fabric
PAMU
PAMU
PAMU (peripheral access management unit)
FMan
SEC
PME
QMan
BMan
RMan
Parse, classify,
distribute
Buffer
1/10G 1/10G
FMan
Parse, classify,
distribute
Buffer
1/10G 1/10G
InterlakenLA-1
Real-time
debug
3x DMA
SATA 2.0
SATA 2.0
Watch point
cross-
trigger
Perf
Trace
Monitor
sRIO
sRIO
PCle
PCle
PCle
PCle
1G 1G 1G
1G 1G 1G
1G 1G 1G
1G 1G 1G
Aurora
16 lanes up to 10 GHz SerDes
16 lanes up to 10 GHz SerDes
2
1146D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
T4240
2.
2.1
PIN ASSIGNMENTS
1932 ball layout diagrams
This table shows the complete view of the T4240 ball map. Figure 2‐2, Figure 2‐3, Figure 2‐4, and Figure
2‐5 show quadrant views of the ballmap.
Figure 2‐1.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
BA
BB
BC
BD
Complete BGA Map for the T4240
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
B
C
D
E
F
G
H
SEE DETAIL A
SEE DETAIL B
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
SEE DETAIL C
SEE DETAIL D
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
BA
BB
BC
BD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DDR Interface 1
DDR Interface 2
DDR Interface 3
IFC
DUART
I2C
eSPI
eSDHC
MPIC
LP Trust
Trust
System Control
ASLEEP
Clocking
DDR Clocking
Debug
DFT
JTA G
SerDes 1
SerDes 2
SerDes 3
SerDes 4
USB PHY 1 and 2
USB CL K
IEEE1588
Ethernet MI 1
Ethernet MI 2
Ethernet Cont. 1
Ethernet Cont. 2
DMA
Analog signals
Powe r
Ground
No Connects
3
1146D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
T4240
Figure 2‐2.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
G1VDD
[04]
D1_
MA
[08]
D1_
MA
[06]
D1_
MA
[04]
G1VDD
[08]
D1_
MA
[01]
D1_
MDIC
[1]
D1_
MCK
_B[3]
G1VDD
[10]
D1_
MCK
[1]
D1_
MCK
_B[1]
D1_
MCK
_B[2]
G1VDD
[12]
D1_
MAPAR_
OUT
D1_
MA
[10]
D1_
MBA
[0]
G1VDD
[16]
D1_
MCS
_B[2]
D1_
MCS
_B[0]
D1_
MODT
[0]
G1VDD
[22]
Detail A
2
G1VDD
[01]
D1_
MA
[11]
D1_
MA
[07]
G1VDD
[07]
D1_
MA
[05]
D1_
MA
[03]
D1_
MA
[02]
G1VDD
[09]
D1_
MCK
[3]
D1_
MCK
[0]
D1_
MCK
_B[0]
G1VDD
[11]
D1_
MCK
[2]
D1_
MDIC
[0]
D1_
MA
[00]
G1VDD
[13]
D1_
MBA
[1]
D1_
MRAS_B
3
D1_
MA
[12]
D1_
MA
[09]
GND_
DET
[1]
GND
[015]
4
D1_
MAPAR_
ERR_B
G1VDD
[05]
5
D1_
MBA
[2]
D1_
MA
[14]
GND
[010]
D1_
MDQ
[06]
D1_
MDQ
[07]
D1_
MDQS
[00]
D1_
MDQS
[01]
D1_
MDQS
_B[01]
GND
[045]
D1_
MDQ
[28]
D1_
MDQ
[24]
D1_
MDM
[3]
D1_
MDQS
_B[03]
D1_
MDQ
[30]
D1_
MDQ
[26]
D1_
MECC
[4]
D1_
MECC
[0]
D1_
MDM
[8]
D1_
MDQS
_B[08]
D1_
MECC
[6]
D1_
MECC
[2]
D1_
MDQ
[52]
6
G1VDD
[02]
D1_
MA
[15]
GND
[011]
D1_
MDQS
_B[09]
GND
[022]
D1_
MDQS
_B[00]
GND
[035]
D1_
MDQS
_B[10]
D1_
MDQ
[14]
GND
[052]
7
D1_
MCKE
[0]
D1_
MCKE
[2]
GND
[012]
D1_
MDM
[0]
D1_
MDQ
[01]
D1_
MDQ
[00]
D1_
MDQ
[09]
D1_
MDM
[1]
GND
[046]
D1_
MDQ
[21]
D1_
MDQ
[17]
D1_
MDQS
_B[11]
D1_
MDQS
[02]
D1_
MDQ
[23]
D1_
MDQ
[19]
D1_
MDQ
[36]
D1_
MDQ
[32]
D1_
MDM
[4]
D1_
MDQS
_B[04]
D1_
MDQ
[38]
D1_
MDQ
[34]
D1_
MDQ
[48]
8
D1_
MCKE
[3]
D1_
MCKE
[1]
GND
[013]
D1_
MDQ
[05]
D1_
MDQ
[04]
GND
[027]
D1_
MDQ
[13]
D1_
MDQ
[12]
D1_
MDQ
[08]
D1_
MDQ
[20]
D1_
MDQ
[16]
D1_
MDM
[2]
D1_
MDQS
_B[02]
D1_
MDQ
[22]
D1_
MDQ
[18]
D1_
MDQ
[37]
D1_
MDQ
[33]
D1_
MDQS
_B[13]
D1_
MDQS
[04]
D1_
MDQ
[39]
D1_
MDQ
[35]
GND
[184]
9
G1VDD
[03]
10 11 12 13 14 15 16 17 18 19 20 21 22
EC2_
RXD
[0]
EC2_
RX_
CLK
EC2_
RX_
DV
EC2_
RXD
[3]
EC2_
GTX_
CLK125
EC2_
TXD
[1]
EC2_
TX_
EN
EC2_
GTX_
CLK
UART2_
SOUT
EC2_
RXD
[1]
GND
[002]
EC2_
RXD
[2]
EC2_
TXD
[0]
GND
[024]
EC2_
TXD
[2]
EC2_
TXD
[3]
GND
[040]
EC1_
RXD
[2]
EC1_
RX_
CLK
EC1_
RXD
[0]
EC1_
GTX_
CLK125
EC1_
RXD
[1]
EC1_
GTX_
CLK
EC1_
RXD
[3]
EC1_
TXD
[0]
TSEC_A
LARM_O
UT2
EC1_
TXD
[1]
EC1_
TXD
[2]
EC1_
TXD
[3]
IIC4_
SCL
EC1_
RX_
DV
GND
[003]
EC1_
TX_
EN
EMI2_
MDC
TSEC_C
LK_IN
S1GND
[05]
S1GND
[01]
SD1_
RX
[1]
SD1_
RX
_B[1]
S1GND
[11]
S1GND
[02]
SD1_
RX
[3]
SD1_
RX
_B[3]
S1GND
[12]
S1GND
[03]
SD1_
RX
[5]
SD1_
RX
_B[5]
S1GND
[13]
S1GND
[04]
SD1_
RX
[7]
SD1_
RX
_B[7]
S1GND
[14]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
G1VDD
[06]
S1GND
[06]
SD1_
RX
[0]
SD1_
RX
_B[0]
S1GND
[21]
S1GND
[07]
SD1_
RX
[2]
SD1_
RX
_B[2]
S1GND
[23]
S1GND
[08]
SD1_
RX
[4]
SD1_
RX
_B[4]
S1GND
[25]
S1GND
[09]
SD1_
RX
[6]
SD1_
RX
_B[6]
S1GND
[27]
GND
[009]
D1_
MDQ
[02]
D1_
MDQ
[03]
GND
[026]
D1_
MDQ
[10]
D1_
MDQ
[11]
D1_
MDQ
[15]
D1_
MDQ
[29]
D1_
MDQ
[25]
D1_
MDQS
_B[12]
D1_
MDQS
[03]
D1_
MDQ
[31]
D1_
MDQ
[27]
D1_
MECC
[5]
D1_
MECC
[1]
D1_
MDQS
_B[17]
D1_
MDQS
[08]
D1_
MECC
[7]
D1_
MECC
[3]
GND
[183]
GND
[014]
S1GND
[10]
GND
[016]
S1GND
[15]
S1GND
[16]
S1GND
[17]
S1GND
[18]
S1GND
[19]
GND
[021]
GND
[023]
EMI2_
MDIO
S1GND
[20]
TSEC_C
LK_OUT
S1GND
[22]
SD1_
TX
[1]
SD1_
TX
_B[1]
X1GND
[11]
S1GND
[24]
SD1_
TX
[3]
SD1_
TX
_B[3]
X1GND
[12]
S1GND
[26]
SD1_
TX
[5]
SD1_
TX
_B[5]
X1GND
[13]
S1GND
[28]
SD1_
TX
[7]
SD1_
TX
_B[7]
X1GND
[14]
GND
[025]
GND
[028]
GND
[029]
X1GND
[01]
X1GND
[02]
X1GND
[03]
X1GND
[04]
GND
[034]
GND
[036]
EMI1_
MDC
X1GND
[05]
X1GND
[06]
SD1_
TX
[0]
SD1_
TX
_B[0]
X1VDD
[1]
X1GND
[07]
SD1_
TX
[2]
SD1_
TX
_B[2]
X1VDD
[3]
AVDD_
SD1_
PLL1
X1GND
[23]
X1GND
[08]
SD1_
TX
[4]
SD1_
TX
_B[4]
X1VDD
[5]
X1GND
[09]
SD1_
TX
[6]
SD1_
TX
_B[6]
X1VDD
[7]
AVDD_
SD1_
PLL2
X1GND
[24]
SD1_
REF_
CLK2_B
SD1_
REF_
CLK2
S1GND
[40]
GND
[038]
GND
[039]
EMI1_
MDIO
X1GND
[10]
GND
[044]
GND
[047]
UART2_
SIN
GND
[048]
TSEC_A
LARM_O
UT1
TSEC_P
ULSE_O
UT2
GND
[065]
X1GND
[15]
X1GND
[16]
X1GND
[17]
X1GND
[18]
X1GND
[19]
GND
[051]
GND
[053]
UART2_
RTS_B
UART2_
CTS_B
X1GND
[20]
X1VDD
[2]
SD1_
PLL1_
TPD
SD1_
IMP_
CAL_RX
S1GND
[31]
X1VDD
[4]
AGND_
SD1_PLL
1
SD1_
PLL1_
TPA
S1GND
[32]
SD1_
REF_
CLK1
S1GND
[37]
X1VDD
[6]
AGND_
SD1_PLL
2
SD1_
PLL2_
TPA
S1GND
[34]
X1VDD
[8]
SD1_
PLL2_
TPD
SD1_
IMP_
CAL_TX
S1GND
[35]
GND
[057]
GND
[058]
GND
[059]
UART1_
SOUT
GND
[060]
LVDD
[1]
TSEC_P
ULSE_O
UT1
TSEC_T
RIG_IN
2
GND
[078]
X1GND
[21]
X1GND
[22]
GND
[062]
GND
[063]
GND
[064]
UART1_
RTS_B
UART1_
SIN
S1GND
[29]
TSEC_T
RIG_IN
1
GND
[079]
S1GND
[30]
GND
[069]
GND
[070]
GND
[071]
IIC2_
SCL
UART1_
CTS_B
IIC3_
SCL
S1VDD
[1]
S1GND
[33]
SD1_
REF_
CLK1_B
S1GND
[38]
GND
[074]
GND
[075]
GND
[076]
IIC2_
SDA
GND
[077]
IIC4_
SDA
SENSE
VDD_
CA
GND
[093]
D1_
MDQ
[41]
GND
[116]
IIC3_
SDA
SENSE
GND_
CA
AVDD_
D1
GND
[080]
S1GND
[36]
S1VDD
[2]
S1VDD
[3]
GND
[083]
GND
[084]
GND
[085]
IIC1_
SCL
IIC1_
SDA
DVDD
[1]
DVDD
[2]
LVDD
[2]
LVDD
[3]
S1GND
[39]
S1GND
[41]
GND
[088]
GND
[089]
GND
[090]
D1_
MDQ
[44]
GND
[115]
GND
[091]
D1_
MDQ
[45]
D1_
MDM
[5]
D1_
MDQS
_B[05]
D1_
MDQ
[46]
GND
[167]
D1_
MDM
[7]
GND
[092]
D1_
MDQ
[40]
D1_
MDQS
_B[14]
D1_
MDQS
[05]
D1_
MDQ
[47]
GND
[168]
D1_
MDQS
_B[07]
GND
[094]
G1VDD
[14]
VDD
[01]
GND
[095]
NC
[45]
S1VDD
[4]
S1VDD
[5]
S1VDD
[6]
S1VDD
[7]
GND
[099]
GND
[100]
GND
[101]
GND
[102]
G1VDD
[15]
GND
[103]
VDD
[02]
GND
[104]
VDD
[03]
GND
[105]
VDD
[04]
GND
[106]
GND
[113]
GND
[114]
D1_
MVREF
GND
[117]
G1VDD
[17]
VDD
[09]
GND
[118]
VDD
[10]
GND
[119]
VDD
[11]
GND
[120]
VDD
[12]
D1_
MWE_B
GND
[128]
GND
[129]
GND
[130]
GND
[131]
D1_
MDQ
[42]
GND
[169]
D1_
MDQ
[62]
GND
[132]
D1_
MDQ
[43]
GND
[170]
D1_
MDQ
[58]
GND
[133]
G1VDD
[18]
GND
[134]
VDD
[16]
GND
[135]
VDD
[17]
GND
[136]
VDD
[18]
GND
[137]
G1VDD
[19]
GND
[145]
GND
[146]
GND
[147]
D1_
MDQ
[61]
D1_
MDQ
[60]
GND
[148]
G1VDD
[20]
VDD
[23]
GND
[149]
VDD
[24]
GND
[150]
VDD
[25]
GND
[151]
VDD
[26]
D1_
MCAS_B
D1_
MODT
[2]
GND
[165]
GND
[166]
D1_
MDQ
[53]
GND
[171]
G1VDD
[21]
GND
[172]
VDD
[30]
GND
[173]
VDD
[31]
GND
[174]
VDD
[32]
GND
[175]
GND
[182]
GND
[185]
G1VDD
[23]
VDD
[37]
GND
[186]
VDD
[38]
GND
[187]
VDD
[39]
GND
[188]
VDD
[40]
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
DDR Interface 3
IFC
DUART
DDR Interface 1
DDR Interface 2
I2C
eSPI
eSDHC
MPIC
LP Trust
Trust
System Control
ASLEEP
Clocking
DDR Clocking
Debug
DFT
JTA G
SerDes 1
SerDes 2
SerDes 3
SerDes 4
USB PHY 1 and 2
USB CL K
IEEE1588
Ethernet MI 1
Ethernet MI 2
Ethernet Cont. 1
Ethernet Cont. 2
DMA
Analog signals
Powe r
Ground
No Connects
4
1146D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
T4240
Figure 2‐3.
Detail B
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
S2GND
[01]
SD2_
RX
[1]
SD2_
RX
_B[1]
S2GND
[11]
S2GND
[02]
SD2_
RX
[3]
SD2_
RX
_B[3]
S2GND
[12]
S2GND
[03]
SD2_
RX
[5]
SD2_
RX
_B[5]
S2GND
[13]
S2GND
[04]
SD2_
RX
[7]
SD2_
RX
_B[7]
S2GND
[14]
S2GND
[05]
USB2_
DRV
VBUS
USB2_
PWR
FAULT
USB2_
VBUS
CLMP
USB_
AGND
[1]
USB1_
DRV
VBUS
USB1_
PWR
FAULT
USB1_
VBUS
CLMP
USB2_
UID
USB_
AGND
[2]
USB_
HVDD
[1]
USB1_
UID
USB_
AGND
[4]
USB_
HVDD
[2]
USB_
OVDD
[2]
FA_
ANALOG_
G_V
FA_
ANALOG_
PIN
NC
[51]
SDHC_
CLK
SDHC_
CD_B
SDHC_
DAT
[0]
SDHC_
DAT
[1]
GND
[017]
SDHC_
DAT
[2]
SDHC_
DAT
[3]
SPI_
CS
_B[0]
HRESET_
B
SPI_
CS
_B[1]
GND
[005]
SPI_
CS
_B[2]
SPI_
CS
_B[3]
SPI_
MOSI
IFC_
CLK2
IFC_
A
[30]
GND
[006]
IFC_
A
[29]
IFC_
A
[28]
IFC_
AD
[30]
GND
[032]
IFC_
AD
[26]
GND
[043]
IFC_
AD
[20]
IFC_
AD
[18]
GND
[061]
IFC_
AD
[14]
IFC_
AD
[12]
GND
[082]
IFC_
AD
[08]
IFC_
AD
[06]
GND
[112]
IFC_
AD
[02]
IFC_
AD
[00]
GND
[161]
D3_
MDQS
_B[16]
D3_
MDM
[7]
IFC_
A
[27]
IFC_
A
[26]
IFC_
CS
_B[7]
GND
[019]
IFC_
AD
[29]
IFC_
AD
[27]
IFC_
AD
[24]
IFC_
AD
[22]
IFC_
AD
[21]
IFC_
AD
[19]
IFC_
AD
[16]
IFC_
AD
[15]
IFC_
AD
[13]
IFC_
AD
[10]
IFC_
AD
[09]
IFC_
AD
[07]
IFC_
AD
[04]
IFC_
AD
[03]
IFC_
AD
[01]
GND
[162]
D3_
MDQ
[57]
D3_
MDQ
[56]
IFC_
CS
_B[6]
IFC_
CS
_B[5]
IFC_
CS
_B[4]
IFC_
AD
[31]
IFC_
AD
[28]
GND
[033]
IFC_
AD
[25]
IFC_
AD
[23]
GND
[049]
IFC_
CS
_B[3]
GND
[007]
GND
[001]
IFC_
CS
_B[2]
IFC_
CS
_B[0]
GND
[020]
A
GND
[008]
IFC_
CS
_B[1]
IFC_
WE
_B[3]
IFC_
WE
_B[0]
IFC_
WP
_B[0]
S2GND
[06]
SD2_
RX
[0]
SD2_
RX
_B[0]
S2GND
[20]
S2GND
[07]
SD2_
RX
[2]
SD2_
RX
_B[2]
S2GND
[22]
S2GND
[08]
SD2_
RX
[4]
SD2_
RX
_B[4]
S2GND
[24]
S2GND
[09]
SD2_
RX
[6]
SD2_
RX
_B[6]
S2GND
[26]
S2GND
[10]
GND
[004]
SPI_
CLK
IFC_
CLK0
IFC_
A
[31]
IFC_
PAR
[1]
IFC_
PAR
[0]
IFC_
PAR
[2]
NC
[04]
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
S2GND
[15]
USB_
IBIAS_
REXT
X2GND
[01]
SDHC_
WP
SPI_
MISO
NC_
DET
IFC_
WE
_B[2]
IFC_
OE_B
IFC_
RB
_B[1]
IFC_
TE
S2GND
[16]
S2GND
[17]
S2GND
[18]
S2GND
[19]
SDHC_
CMD
GND
[018]
S2GND
[21]
SD2_
TX
[1]
SD2_
TX
_B[1]
X2GND
[12]
S2GND
[23]
SD2_
TX
[3]
SD2_
TX
_B[3]
X2GND
[13]
S2GND
[25]
SD2_
TX
[5]
SD2_
TX
_B[5]
X2GND
[14]
S2GND
[27]
SD2_
TX
[7]
SD2_
TX
_B[7]
X2GND
[15]
SCAN_
TMP_
IFC_
USBCLK
MODE_B
DETECT_B NDDQS
IFC_
PERR_B
IFC_
PAR
[3]
NC
[03]
IFC_
CLE
IFC_
RB
_B[0]
GND
[037]
IFC_
NDDDR_
CLK
X2GND
[02]
X2GND
[03]
X2GND
[04]
X2GND
[05]
X2GND
[06]
GND
[030]
TEST_ PORESET_
SEL_B
B
GND
[031]
X2GND
[07]
SD2_
TX
[0]
SD2_
TX
_B[0]
X2VDD
[1]
SD2_
PLL1_
TPD
SD2_
IMP_
CAL_RX
S2GND
[29]
X2GND
[08]
SD2_
TX
[2]
SD2_
TX
_B[2]
X2VDD
[3]
AGND_
SD2_PLL
1
SD2_
PLL1_
TPA
S2GND
[30]
X2GND
[09]
SD2_
TX
[4]
SD2_
TX
_B[4]
X2VDD
[5]
AGND_
SD2_PLL
2
SD2_
PLL2_
TPA
S2GND
[32]
SD2_
REF_
CLK2
S2GND
[39]
X2GND
[10]
SD2_
TX
[6]
SD2_
TX
_B[6]
X2VDD
[7]
SD2_
PLL2_
TPD
SD2_
IMP_
CAL_TX
X2GND
[25]
USB_
SVDD
[1]
PROG_
SFP
X2GND
[11]
RESET_
REQ_B
ASLEEP
NC
[01]
NC
[02]
IFC_BCTL
X2GND
[16]
NC
[05]
GND
[041]
NC
[06]
NC
[07]
GND
[042]
NC
[08]
IFC_
CLK1
IFC_
AVD
X2GND
[17]
X2GND
[18]
X2GND
[19]
X2GND
[20]
USB1_
UDM
NC
[09]
NC
[10]
NC
[11]
NC
[12]
NC
[13]
NC
[14]
TRST_B
TDI
GND
[050]
X2VDD
[2]
AVDD_
SD2_
PLL1
X2GND
[23]
SD2_
REF_
CLK1_B
SD2_
REF_
CLK1
S2GND
[36]
X2VDD
[4]
X2VDD
[6]
AVDD_
SD2_
PLL2
X2GND
[24]
X2VDD
[8]
USB1_
UDP
USB_
AGND
[3]
USB2_
UDM
GND
[054]
NC
[15]
NC
[16]
GND
[055]
NC
[17]
NC
[18]
TMS
TDO
GND
[056]
TCK
X2GND
[21]
X2GND
[22]
NC
[19]
NC
[20]
NC
[21]
NC
[22]
NC
[23]
NC
[24]
IFC_
AD
[17]
GND
[067]
DMA2_
DREQ
_B[0]
IFC_
AD
[11]
GND
[087]
EVT_B
[4]
EVT_B
[3]
CKSTP_
OUT_B
S2GND
[28]
X2VDD
[9]
USB_
AGND
[5]
USB_
SVDD
[2]
OVDD
[1]
NC
[25]
GND
[066]
NC
[26]
NC
[27]
NC
[28]
NC
[29]
EVT_B
[2]
EVT_B
[1]
GND
[068]
S2GND
[31]
SD2_
REF_
CLK2_B
S2GND
[38]
S2GND
[33]
USB2_
UDP
USB_
OVDD
[1]
GND
[086]
NC
[30]
NC
[31]
NC
[32]
NC
[33]
GND
[072]
NC
[34]
EVT_B
[0]
DMA2_
DDONE
_B[0]
IRQ
[05]
GND
[073]
DMA1_
DREQ
_B[0]
DMA1_
DACK
_B[0]
GND
[098]
CLK_
OUT
DMA2_
DACK
_B[0]
DMA1_
DDONE
_B[0]
IRQ
[08]
S2VDD
[1]
S2VDD
[2]
S2GND
[34]
GND
[081]
NC
[35]
NC
[36]
NC
[37]
NC
[38]
NC
[39]
S2GND
[35]
S2GND
[37]
VDD_
LP
FA_
VL
NC
[40]
NC
[41]
NC
[42]
NC
[43]
NC
[44]
S2VDD
[3]
S2VDD
[4]
S2VDD
[5]
LP_
S2VDD
AVDD_
TMP_
[6]
PLAT
DETECT_B
GND
[108]
VDD
[07]
GND
[109]
PROG_
MTR
OVDD
[2]
GND
[096]
NC
[46]
NC
[47]
NC
[48]
NC
[49]
GND
[097]
NC
[50]
IRQ_
OUT_B
IFC_
AD
[05]
GND
[127]
IRQ
[07]
VDD
[05]
GND
[107]
VDD
[06]
VDD
[08]
OVDD
[3]
GND
[110]
GND
[111]
SYSCLK
NC
[52]
NC
[53]
NC
[54]
NC
[55]
IRQ
[11]
IRQ
[02]
IRQ
[04]
GND
[121]
VDD
[13]
GND
[122]
VDD
[14]
GND
[123]
VDD
[15]
GND
[124]
OVDD
[4]
GND
[125]
TH_
VDD
RTC
GND
[126]
NC
[56]
NC
[57]
NC
[58]
NC
[59]
IRQ
[09]
IRQ
[00]
IRQ
[01]
VDD
[19]
GND
[138]
VDD
[20]
GND
[139]
VDD
[21]
GND
[140]
VDD
[22]
OVDD
[5]
GND
[141]
TH_
TPA
SENSE
VDD_
PL
SENSE
GND_
PL
GND
[194]
GND
[142]
NC
[60]
NC
[61]
NC
[62]
GND
[143]
NC
[63]
IRQ
[06]
IRQ
[03]
GND
[144]
IRQ
[10]
GND
[152]
VDD
[27]
GND
[153]
VDD
[28]
GND
[154]
VDD
[29]
GND
[155]
OVDD
[6]
GND
[156]
SENSE
TD1_
VDD_
CATHODE
CC
SENSE
GND_
CC
GND
[195]
TD1_
ANODE
GND
[157]
GND
[158]
D3_
MDQ
[59]
D3_
MDQ
[58]
GND
[159]
D3_
MDQ
[63]
D3_
MDQ
[62]
GND
[160]
D3_
MDQS
[07]
D3_
MDQS
_B[07]
GND
[163]
D3_
MDQ
[61]
D3_
MDQ
[60]
GND
[164]
G3VDD
[01]
D3_
MODT
[1]
G3VDD
[04]
G3VDD
[02]
D3_
MODT
[3]
D3_
MA
[13]
VDD
[33]
GND
[176]
VDD
[34]
GND
[177]
VDD
[35]
GND
[178]
VDD
[36]
OVDD
[7]
GND
[179]
GND
[180]
GND
[181]
GND
[189]
VDD
[41]
GND
[190]
VDD
[42]
GND
[191]
VDD
[43]
GND
[192]
G3VDD
[03]
GND
[193]
GND
[196]
GND
[197]
GND
[198]
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
DDR Interface 1
DDR Interface 2
DDR Interface 3
IFC
DUART
I2C
eSPI
eSDHC
MPIC
LP Trust
Trust
System Control
ASLEEP
Clocking
DDR Clocking
Debug
DFT
JTA G
SerDes 1
SerDes 2
SerDes 3
SerDes 4
USB PHY 1 and 2
USB CL K
IEEE1588
Ethernet MI 1
Ethernet MI 2
Ethernet Cont. 1
Ethernet Cont. 2
DMA
Analog signals
Powe r
Ground
No Connects
5
1146D–HIREL–10/18
Teledyne e2v Semiconductors SAS 2018
京公网安备 11010802033920号
EEWORLD
