CXA2000Q
Y/C/RGB/D for PAL/NTSC Color TVs
Description
The CXA2000Q is a bipolar IC which integrates the
luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC/PAL
system color TVs onto a single chip. This IC includes
deflection processing functions for wide-screen TVs,
and is also equipped with a SECAM decoder
interface, making it possible to construct a TV
system that supports multiple color systems.
64 pin QFP (Plastic)
Features
•
I
2
C bus compatible
•
Compatible with both PAL and NTSC systems
(also compatible with SECAM if a SECAM decoder is connected)
•
Built-in deflection compensation circuit capable of supporting various wide modes
•
Countdown system eliminates need for H and V oscillator frequency adjustment
•
Automatic identification of 50/60Hz vertical frequency (forced control possible)
•
Non-interlace display support (even/odd selectable)
•
Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible)
•
Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible)
•
Non-adjusting Y/C block filter
•
One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both
analog and digital inputs)
•
Built-in AKB circuit
•
Support for forcing YS1 off
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings
(Ta = 25°C, SGND, DGND = 0V)
•
Supply voltage
SV
CC
1, 2, DV
CC
1, 2
–0.3 to 12
V
•
Operating temperature
Topr
–20 to +65
°C
•
Storage temperature
Tstg
–65 to +150
°C
•
Allowable power dissipation
P
D
1.7
W
(when mounted on 50mm
×
50mm board)
•
Voltages at each pin
–0.3 to SV
CC
1, SV
CC
2,
DV
CC
1, DV
CC
2 + 0.3 V
Operating Conditions
Supply voltage
SV
CC
1, 2
DV
CC
1, 2
9.0 ± 0.5
9.0 ± 0.5
V
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96103-ST
Block Diagram
EXT SYNC IN
VM
DCTRAN
VSFIL
HSIN
SYNCOUT
SDA
SCL
BLHOLD
VSIN
56
52
41
39
51
48
2Vp-p
49
54
47
38
H SYNC
SEP
32f
H
VCO
PHASE
DET
V SYNC
SEP
GATE
PHASE
DET.
1/32
2f
H
H POSI
AFC
C MODE
Sand
Castle
PHASE
SHIFT
50
45
46
40
AFCFIL
CERA
AFCPIN/
HOFF
L2FIL
36 DV
CC
1
44 DV
CC
2
42 DGND
H.DRIVE
37 HD OUT
10 SCPOUT
SCP BGR/BGF
30 VTIM
34 VAGCSH
VPOSI, VOFF,
VSIZE
35 SAWOSC
6dB
VM OFF
EXT
SYNC
CV/YC
DLSHARP
V FREQ
50/60 ID
SHARP
NESS
D PIC
GATE
Count Down
525/625
PRE/OVER
TOT
TOT
INTERLACE
PIC
D-COL
γ
KILLER
DET
YS1 OFF
DEM
PAL
ID
fsc
ID
Y/C
MIX
YS
SW
YS/YM
SW
PIC
OSD
MIX
INTER
-LACE
DC
TRAN AGING D PIC
STATUS
SUB CONT
DL
DC
TRAN
CLP
TRAP OFF
CVIN 53
S
SEP
1Vp-p
YIN 55
VIDEO
SW
SUB
CONT
TRAP
ACC
DET
1Vp-p
YS1
YS2
YM
RSH
B1IN
IREF
R2IN
X358
X443
R1IN
G1IN
YOUT
YRET
G2IN
B2IN
APCFIL
ABLFIL
FSCOUT
SECAMREF
–(R-Y) OUT
–(B-Y) OUT
–(R-Y) IN
–(B-Y) IN
ABLIN/
VCOMP
GSH
BSH
–2–
fsc R-Y
COLOR
& AXIS
COL
3
4
7
5
6
8
11 12 13 14
fsc B-Y
CLP
CLP
15 16 17 18 19
DEM
AXIS
CIN 57
ACC
TRAP F0
VD+OUT
32 /VPROT
WIDE
Sawtooth
VD–OUT
Gen.
31 /VPROT
VLIN, SCORR
33 E-WOUT
BRT GB DRV
WIDE
Parabola
Gen.
GB CUT
SUB COLOR
COLOR SW
22 ROUT
D-
COL
γ
BRT
GB
DRV
CUT
OFF
BLK
24 GOUT
26 BOUT
HV
COMP
DIG
ABL
29
28
EHT H, V
27 IKIN
AKB
AKB OFF
21 23 25
SV
CC
1 59
SV
CC
2 20
APC
PAL/
NTSC
SGND1 2
SGND2 9
HUE
IREF
VCO
HUE
XTAL
43
60
62
61
64
1
CXA2000Q
CXA2000Q
Pin Configuration
AFCPIN/HOFF
SYNCOUT
SAWOSC
VAGCSH
AFCFIL
HDOUT
DGND
CERA
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
BLHOLD 52
CVIN 53
DCTRAN 54
YIN 55
EXT SYNC IN 56
CIN 57
TEST 58
SV
CC
1 59
APCFIL 60
X443 61
X358 62
NC 63
FSCOUT 64
L2FIL
DV
CC
1
E-WOUT
HSIN
VSIN
VSFIL
DV
CC
2
SDA
SCL
VM
IREF
32 VD+OUT/VPROT
31 VD–OUT/VPROT
30 VTIM
29 ABLFIL
28 ABLIN/VCOMP
27 IKIN
26 BOUT
25 BSH
24 GOUT
23 GSH
22 ROUT
21 RSH
20 SV
CC
2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SECAMREF
–(R-Y) OUT
–(B-Y) OUT
–(R-Y) IN
–(B-Y) IN
SGND1
SGND2
YOUT
YRET
–3–
SCPOUT
G1IN
G2IN
R1IN
R2IN
B1IN
B2IN
YS1
YS2
YM
CXA2000Q
Pin Description
Pin
No.
Symbol
Equivalent circuit
Description
6k
20p
1
SECAMREF
1
250µA
7.2V
SECAM decoder interface. This pin
serves as both a 4.43MHz output and as
a SECAM identification input/output pin.
2
SGND1
—
GND for Y/C block.
200µA
3
4
–(R-Y) OUT
–(B-Y) OUT
3
4
Color difference signal outputs. Go to
high impedance when the SECAM
system is detected.
Standard output levels for 75% CB:
B-Y: 0.665Vp-p
R-Y: 0.525Vp-p
500
5
YOUT
5
30k
400µA
Luminance signal output.
Black level is 3.5VDC.
Standard output level for 100 IRE input:
1Vp-p
6
YRET
6
1.5k
70k
Luminance signal input.
Clamped to 4.8V at the burst timing.
Standard input level for 100 IRE input:
1Vp-p
7
8
–(R-Y) IN
–(B-Y) IN
7
8
1.5k
70k
Color difference signal inputs.
Clamped to 5.5V at the burst timing.
Standard input levels for 75% CB:
B-Y: 1.33Vp-p
R-Y: 1.05Vp-p
9
SGND2
–4–
GND for the RGB block.
CXA2000Q
Pin
No.
Symbol
Equivalent circuit
Description
1k
10
SCPOUT
10
10k
1k
Sand castle pulse output. The 0 to 5V
BGP pulse, the phase of which is
controlled through the bus, is
superimposed with the 0 to 2V H and
VBLK pulse for output.
100µA
11
YS1
11
40k
YSSW control input.
When YS is high, the RGB1 block signal
is selected; when YS is low, the Y/C block
is selected. This function can be disabled
by the YS1OFF setting for the I
2
C bus.
VILMAX = 0.4V
VIHMIN = 1.0V
200
12
13
14
R1IN
G1IN
B1IN
12
13
14
30k
Analog R, G and B signal inputs.
Input a 0.7Vp-p (no sync, 100 IRE) signal
via a capacitor.
The signal is clamped to 5.7V at the burst
timing of the signal input to the HSIN
input pin (Pin 47).
100µA
15
YS2
15
40k
YS/YMSW YS control input.
When YS is high, the RGB2 block signal
is selected; when YS is low, the YSSW
output signal is selected.
VILMAX = 0.4V
VIHMIN = 1.0V
100µA
16
YM
16
40k
YS/YMSW YM control input.
When YM is high, the YSSW output
signal is attenuated by 9.6dB.
VILMAX = 0.4V
VIHMIN = 1.0V
–5–
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