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CSPST16-470F

Description
CHIP SCALE SERIES TERMINATION ARRAY
File Size51KB,4 Pages
ManufacturerCALMIRCO
Websitehttp://www.calmicro.com/
Download Datasheet View All

CSPST16-470F Overview

CHIP SCALE SERIES TERMINATION ARRAY

CALIFORNIA MICRO DEVICES
CSPST
Chip Scale Series Termination Array
Features
• 8 or 16 integrated high frequency series
terminations
• Ultra small footprint Chip Scale Package
• Ceramic substrate
• 0.35mm Eutectic Solder Bumps, 0.65mm pitch
Applications
• Series resistive bus termination
• Isolated resistor array
Product Description
The CSPST is a high performance Integrated Passive
Device (IPD) which provides series terminations suitable
for use in high speed bus applications. Eight (8) or
sixteen (16) series termination versions are provided.
These resistors provide excellent high frequency
performance in excess of 3GHz and are manufactured to
an absolute tolerance as low as ±1%. The Chip Scale
Package provides an ultra small footprint for this IPD
and provides minimal parasitics compared to conven-
tional packaging. Typical bump inductance is less than
25pH. The large solder bumps and ceramic substrate
allow for standard attachment to laminate printed circuit
boards without the use of underfill.
SCHEMATIC DIAGRAMS
D
R1
R1
R1
R1
D
R1
R1
R1
R1
R1
R1
R1
R1
C
C
B
R1
A
1
2
3
4
R1
R1
R1
B
R1
A
1
2
3
4
5
6
7
8
R1
R1
R1
R1
R1
R1
R1
CSPST08
CSPST16
S TA N D A R D VA L U E S
Re s i s t o r Va l u e
Ab s o l u t e To l e r a n c e R
TCR of Resi st or s
Powe r Ra t i n g / Re s i s t o r
Op e r a t i n g Te mp e r a t u r e Ra n g e
R1 = 22
Ω,
33
Ω,
39
Ω, 4 7 Ω,
51
Ω,
56
Ω,
± 1 %, ± 5 %
±100ppm
1 0 0 mW
–40°C to 85°C
© 2000 California Micro Devices Corp. All rights reserved.
11/10/2000
C1300700
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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