Features
•
Low Pin Count (LPC) BIOS Device
•
Functions as Firmware Hub for Intel 8XX, E7XXX and E8XXX Chipsets
•
8M Bits of Flash Memory for Platform Code/Data Storage
– Uniform, 64-Kbyte Memory Sectors
– Automated Byte-program and Sector-erase Operations
Two Configurable Interfaces
– Firmware Hub (FWH) Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
Firmware Hub Hardware Interface Mode
– 5-signal Communication Interface Supporting x8 Reads and Writes
– Read and Write Protection for Each Sector Using Software-controlled Registers
– Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other
Sectors
– Five General-purpose Inputs, GPIs, for Platform Design Flexibility
– Operates with 33 MHz PCI Clock and 3.3V I/O
Address/Address Multiplexed (A/A Mux) Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Supports Fast On-board or Out-of-system Programming
Power Supply Specifications
– V
CC
: 3.3V ± 0.3V
– V
PP
: 3.3V and 12V for Fast Programming
Industry-standard Packages
– (40-lead TSOP or 32-lead PLCC)
Green (Pb/Halide-free) Packaging Option
•
•
8-megabit
Firmware Hub
Flash Memory
AT49LW080
•
•
•
•
1. Description
The AT49LW080 is a Flash memory device designed to be compatible with the Intel
82802AC and the Intel 82802AB Firmware Hub (FWH) devices for PC-Bios Applica-
tion. A feature of the AT49LW080 is the nonvolatile memory core. The high-
performance memory is arranged in sixteen 64-Kbyte sectors (see
page 13).
The AT49LW080 supports two hardware interfaces: Firmware Hub (FWH) for in-sys-
tem operation and Address/Address Multiplexed (A/A Mux) for programming during
manufacturing. The IC (Interface Configuration) pin of the device provides the control
between the interfaces. The interface mode needs to be selected prior to power-up or
before return from reset (RST or INIT low to high transition).
An internal Command User Interface (CUI) serves as the control center between the
two device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile
memory. A valid command sequence written to the CUI initiates device automation.
Specifically designed for 3V systems, the AT49LW080 supports read operations at
3.3V and sector erase and program operations at 3.3V and 12V V
PP
. The 12V V
PP
option renders the fastest program performance which will increase factory through-
put, but is not recommended for standard in-system FWH operation in the platform.
With the 3.3V V
PP
option, V
CC
and V
PP
should be tied together for a simple, low-power
3V design. In addition to the voltage flexibility, the dedicated VPP pin gives complete
1966G–FLASH–3/05
data protection when V
PP
≤
V
PPLK
. Internal V
PP
detection circuitry automatically configures the
device for sector erase and program operations. Note that, while current for 12V programming
will be drawn from V
PP
, 3.3V programming board solutions should design such that V
PP
draws
from the same supply as V
CC
, and should assume that full programming current may be drawn
from either pin.
2. Pin Configurations
2.1
32-lead PLCC Top View
FGPI2 [A8]
FGPI3 [A9]
RST [RST]
VPP [VPP]
VCC [VCC]
CLK [R/C]
FGPI4 [A10]
[ ] Designates A/A Mux Mode
2.2
32-lead TSOP Top View
[I/O1] FWH1
[I/O2] FWH2
[GND] GND
[I/O3] FWH3
[I/O4] RFU
[I/O5] RFU
[I/O6] RFU
14
15
16
17
18
19
20
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
IC (V
IL
) [IC(V
IH
)]
GNDa [GNDa]
VCCa [VCCa]
GND [GND]
VCC [VCC]
INIT [OE]
FWH4 [WE]
RFU [RY/BY]
RFU [I/O7]
(NC) NC
[IC (V
IH
)] IC (V
IL
)
[NC] NC
[NC] NC
[NC] NC
[NC] NC
[A10] FGPI4
[NC] NC
[R/C] CLK
[VCC] VCC
[VPP] VPP
[RST] RST
[NC] NC
[NC] NC
[A9] FGPI3
[A8] FGPI2
[A7] FGPI1
[A6] FGPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GNDa [GNDa]
VCCa [VCCa]
FWH4 [WE]
INIT [OE]
RFU [RY/BY]
RFU [I/O7]
RFU [I/O6]
RFU [I/O5]
RFU [I/O4]
VCC [VCC]
GND [GND]
GND [GND]
FWH3 [I/O3]
FWH2 [I/O2]
FWH1 [I/O1]
FWH0 [I/O0]
ID0 [A0]
ID1 [A1]
ID2 [A2]
ID3 [A3]
[ ] Designates A/A Mux Mode
2
AT49LW080
1966G–FLASH–3/05
AT49LW080
2.3
Firmware Hub Interface
The Firmware Hub (FWH) interface is designed to work with the I/O Controller Hub (ICH) during
platform operation.
The FWH interface consists primarily of a five-signal communication interface used to control the
operation of the device in a system environment. The buffers for this interface are PCI compli-
ant. To ensure the effective delivery of security and manageability features, the FWH interface is
the only way to get access to the full feature set of the device. The FWH interface is equipped to
operate at 33 MHz, synchronous with the PCI bus.
2.4
Address/Address Multiplexed Interface
The A/A Mux interface is designed as a programming interface for OEMs to use during mother-
board manufacturing or component pre-programming.
The A/A Mux refers to the multiplexed row and column addresses in this interface. This
approach is required so that the device can be tested and programmed quickly with automated
test equipment (ATE) and PROM programmers in the OEM’s manufacturing flow. This interface
also allows the device to have an efficient programming interface with potentially large future
densities, while still fitting into a 32-pin package. Only basic reads, programming, and erase of
the nonvolatile memory sectors can be performed through the A/A Mux interface. In this mode
FWH features, security features and registers are unavailable. A row/column (R/C) pin deter-
mines which set of addresses “rows or columns” are latched.
3. Block Diagram
WP
TBL
FGPI (4:0)
ID (3:0)
FWH (4:0)
CLK
INIT
OE
R/C
WE
RY/BY
A10 - A0
I/O7 - I/O0
RST
IC
FWH
INTERFACE
FLASH
ARRAY
A/A MUX
INTERFACE
CONTROL
LOGIC
3
1966G–FLASH–3/05
4. Pin Description
Table 4-1
details the usage of each of the device pins. Most of the pins have dual functionality,
with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux functionality for pins is
shown in
bold
in the description box for that pin. All pins are designed to be compliant with volt-
age of V
CC
+ 0.3V max, unless otherwise noted.
Table 4-1.
Pin Description
Interface
Symbol
Type
FWH
A/A Mux
Name and Function
INTERFACE CONFIGURATION PIN:
This pin determines which interface is
operational. This pin is held high to enable the A/A Mux interface. This pin is held low to
enable the FWH interface. This pin must be set at power-up or before return from reset
and not changed during device operation. This pin is pulled down with an internal
resistor, with value between 20 and 100 kΩ. With IC high (A/A Mux mode), this pin will
exhibit a leakage current of approximately 200 µA. This pin may be floated, which will
select FWH mode.
INTERFACE RESET:
Valid for both A/A Mux and FWH interface operations. When
driven low, RST inhibits write operations to provide data protection during power
transitions, resets internal automation, and tri-states pins FWH [3:0] (in FWH interface
mode). RST high enables normal operation. When exiting from reset, the device
defaults to read array mode.
PROCESSOR RESET:
This is a second reset pin for in-system use. This pin is
internally combined with the RST pin. If this pin or RST is driven low, identical operation
is exhibited. This signal is designed to be connected to the chipset INIT signal (Max
voltage depends on the processor. Do not use 3.3V.)
A/A Mux =
OE
CLK
INPUT
X
33 MHz CLOCK for FWH INTERFACE:
This input is the same as the PCI clock and
adheres to the PCI specification.
A/A Mux =
R/C
FWH[3:0]
I/O
X
FWH I/Os:
I/O Communication.
A/A Mux = I/O[3:0]
FWH INPUT:
Input Communication.
A/A Mux =
WE
IDENTIFICATION INPUTS:
These four pins are part of the mechanism that allows
multiple parts to be attached to the same bus. The strapping of these pins is used to
identify the component. The boot device must have ID[3:0] = 0000 and it is
recommended that all subsequent devices should use a sequential up-count strapping
(i.e., 0001, 0010, 0011, etc.). These pins are pulled down with internal resistors, with
values between 20 and 100 kΩ when in FWH mode. Any ID pins that are pulled high will
exhibit a leakage current of approximately 200 µA. Any pins intended to be low may be
left to float. In a single FWH system, all may be left floating.
A/A Mux = A[3:0]
FWH GENERAL PURPOSE INPUTS:
These individual inputs can be used for
additional board flexibility. The state of these pins can be read through FWH registers.
These inputs should be at their desired state before the start of the PCI clock cycle
during which the read is attempted, and should remain at the same level until the end of
the read cycle. They may
only
be used for
3.3V
signals. Unused FGPI pins must
not
be
floated.
A/A Mux = A[10:6]
TOP SECTOR LOCK:
When low, prevents programming or sector erase to the highest
addressable sector (15), regardless of the state of the lock registers TBL high disables
hardware write protection for the top sector, though register-based protection still
applies. The status of TBL does not affect the status of sector-locking registers.
A/A Mux = A4
IC
INPUT
X
X
RST
INPUT
X
X
INIT
INPUT
X
FWH4
INPUT
X
ID[3:0]
INPUT
X
FGPI[4:0]
INPUT
X
TBL
INPUT
X
4
AT49LW080
1966G–FLASH–3/05
AT49LW080
Table 4-1.
Pin Description (Continued)
Interface
Symbol
Type
FWH
A/A Mux
Name and Function
WRITE-PROTECT:
When low, prevents programming or sector erase to all but the
highest addressable sectors (0 - 14), regardless of the state of the corresponding lock
registers. WP-high disables hardware write protection for these sectors, though register-
based protection still applies. The status of TBL does not affect the status of sector-
locking registers.
A/A Mux = A5
LOW-ORDER ADDRESS INPUTS:
Inputs for low-order addresses during read and
write operations. Addresses are internally latched during a write cycle. For the A/A Mux
interface these addresses are latched by R/C and share the same pins as the high-
order address inputs.
DATA INPUT/OUTPUTS:
These pins receive data and commands during write cycles
and transmit data during memory array and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
OUTPUT ENABLE:
Gates the device’s outputs during a read cycle.
ROW-COLUMN ADDRESS SELECT:
For the A/A Mux interface, this pin determines
whether the address pins are pointing to the row addresses, A0 - A10, or to the column
addresses, A11 - A19.
WRITE ENABLE:
Controls writes to the array sectors. Addresses and data are latched
on the rising edge of the WE pulse.
SECTOR ERASE/PROGRAM POWER SUPPLY:
For erasing array sectors or
programming data. V
PP
= 3.3V or 12V. With V
PP
≤
V
PPLK
, memory contents cannot be
altered. Sector erase or program with an invalid V
PP
(see DC Characteristics) produces
spurious results and should not be attempted. V
PP
may only be held at 12V for 80 hours
over the lifetime of the device.
DEVICE POWER SUPPLY:
Internal detection automatically configures the device for
optimized read performance. Do no float any power pins. With V
CC
≤
V
LKO
, all write
attempts to the flash memory are inhibited. Device operations at invalid V
CC
voltages
(see DC Characteristics) produce spurious results and should not be attempted.
GROUND:
Do not float any ground pins.
ANALOG POWER SUPPLY:
This supply should share the same system supply as V
CC
.
ANALOG GROUND:
Should be tied to same plane as GND.
RESERVED FOR FUTURE USE:
These pins are reserved for future generations of this
product and should be connected accordingly. These pins may be left disconnected or
driven. If they are driven, the voltage levels should meet V
IH
and V
IL
requirements.
A/A Mux = I/O[7:4]
NC
RY/BY
OUTPUT
X
X
X
NO CONNECT:
Pin may be driven or floated. If it is driven, the voltage levels should
meet V
IH
and V
IL
. No connects appear only on the 40-lead TSOP package.
READY/BUSY:
Valid only in A/A Mux Mode. This output pin is a reflection of bit 7 in the
status register. This pin is used to determine sector erase or program completion.
WP
INPUT
X
A0 - A10
INPUT
X
I/O0 - I/O7
I/O
X
OE
R/C
INPUT
INPUT
X
X
WE
INPUT
X
V
PP
SUPPLY
X
X
V
CC
SUPPLY
X
X
GND
V
CCa
GNDa
SUPPLY
SUPPLY
SUPPLY
X
X
X
X
X
X
RFU
X
5
1966G–FLASH–3/05
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