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813253AGLFT

Description
Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, TSSOP-24
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size711KB,22 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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813253AGLFT Overview

Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, TSSOP-24

813253AGLFT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts24
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length7.8 mm
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency340 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Master clock/crystal nominal frequency125 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
PRELIMINARY
FEMTOCLOCK™ JITTER ATTENUATOR &
FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
ICS813253
G
ENERAL
D
ESCRIPTION
The ICS813253 is a member of the HiperClockS™
family of high performance clock solutions from
HiPerClockS™
IDT. The ICS813253 is a PLL based synchronous
clock generator that is optimized for Gigabit
Ethernet and PCI-Express clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series. The
first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock frequency multiplier that provides the low
jitter, high frequency Gigabit Ether net or PCI-Express
output clock.
F
EATURES
Three differential LVPECL outputs
One differential input supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 19.6MHz to 136MHz, includ-
ing: 25MHz, 62.5MHz, 100MHz and 125MHz input clocks
Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
Outputs common Gigabit Ethernet or PCI-Express clock rates
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
Absolute pull range: 110ppm
FemtoClock frequency multiplier provides low jitter,
high frequency output
FemtoClock range: 490MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.37ps (typical)
Full 3.3Vsupply, or 3.3V Core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Predivider and output divider multiplication ratios are selected
using device selection control pins. The multiplication ratios are
optimized to support most common clock rates used in Gigabit
Ethernet and PCI-Express applications. The VCXO requires
the use of an external, inexpensive pullable crystal. The VCXO
uses external passive loop filter components which allows
configuration of the PLL loop bandwidth and damping
characteristics.
P
IN
A
SSIGNMENT
ICS813253
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
LF
V
CCA
V
CC
V
CCO
nQ0
Q0
PSEL0
V
EE
PSEL1
XTAL_OUT
XTAL_IN
V
EE
External
Loop Filter Input
nBypass
Pullup
XTAL_OUT
B
LOCK
D
IAGRAM
XTAL_IN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
V
CCO
nQ2
Q2
nQ1
Q1
FSEL0
V
EE
FSEL1
nBypass
CLK
nCLK
Q0
0
CLK
Pulldown
nCLK
Pullup/Pulldown
PSEL0
Pullup
PSEL1
Pullup
FSEL0
Pullup
FSEL1
Pullup
OE
Pullup
Pre-Divider
1, 2.5,
4, 5
Phase
Detector
VCXO
FemtoClock
Frequency
Multiplier x25
1
Output
Divider
2, 4, 5, 25
nQ0
Q1
nQ1
Q2
VCXO Jitter Attenuation PLL
nQ2
IDT
/ ICS
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
1
ICS813253AG REV. A JANUARY 5, 2007

813253AGLFT Related Products

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Description Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, TSSOP-24 Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, TSSOP-24 Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, TSSOP-24 Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, TSSOP-24
Is it lead-free? Lead free Contains lead Lead free Contains lead
Is it Rohs certified? conform to incompatible conform to incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP TSSOP TSSOP
package instruction TSSOP, TSSOP, TSSOP, TSSOP,
Contacts 24 24 24 24
Reach Compliance Code compliant not_compliant compliant not_compliant
ECCN code EAR99 EAR99 EAR99 EAR99
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24
JESD-609 code e3 e3 e3 e0
length 7.8 mm 7.8 mm 7.8 mm 7.8 mm
Number of terminals 24 24 24 24
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Maximum output clock frequency 340 MHz 340 MHz 340 MHz 340 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 240 260 240
Master clock/crystal nominal frequency 125 MHz 125 MHz 125 MHz 125 MHz
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.2 mm
Maximum supply voltage 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) MATTE TIN Matte Tin (Sn) TIN LEAD
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 20 30 20
width 4.4 mm 4.4 mm 4.4 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Base Number Matches 1 1 1 1
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