PRELIMINARY
FEMTOCLOCK™ JITTER ATTENUATOR &
FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
ICS813253
G
ENERAL
D
ESCRIPTION
The ICS813253 is a member of the HiperClockS™
family of high performance clock solutions from
HiPerClockS™
IDT. The ICS813253 is a PLL based synchronous
clock generator that is optimized for Gigabit
Ethernet and PCI-Express clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series. The
first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock frequency multiplier that provides the low
jitter, high frequency Gigabit Ether net or PCI-Express
output clock.
F
EATURES
•
Three differential LVPECL outputs
•
One differential input supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Accepts input frequencies from 19.6MHz to 136MHz, includ-
ing: 25MHz, 62.5MHz, 100MHz and 125MHz input clocks
•
Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
•
Outputs common Gigabit Ethernet or PCI-Express clock rates
•
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
•
Absolute pull range: 110ppm
•
FemtoClock frequency multiplier provides low jitter,
high frequency output
•
FemtoClock range: 490MHz - 680MHz
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.37ps (typical)
•
Full 3.3Vsupply, or 3.3V Core/2.5V output supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Predivider and output divider multiplication ratios are selected
using device selection control pins. The multiplication ratios are
optimized to support most common clock rates used in Gigabit
Ethernet and PCI-Express applications. The VCXO requires
the use of an external, inexpensive pullable crystal. The VCXO
uses external passive loop filter components which allows
configuration of the PLL loop bandwidth and damping
characteristics.
P
IN
A
SSIGNMENT
ICS813253
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
LF
V
CCA
V
CC
V
CCO
nQ0
Q0
PSEL0
V
EE
PSEL1
XTAL_OUT
XTAL_IN
V
EE
External
Loop Filter Input
nBypass
Pullup
XTAL_OUT
B
LOCK
D
IAGRAM
XTAL_IN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
V
CCO
nQ2
Q2
nQ1
Q1
FSEL0
V
EE
FSEL1
nBypass
CLK
nCLK
Q0
0
CLK
Pulldown
nCLK
Pullup/Pulldown
PSEL0
Pullup
PSEL1
Pullup
FSEL0
Pullup
FSEL1
Pullup
OE
Pullup
Pre-Divider
1, 2.5,
4, 5
Phase
Detector
VCXO
FemtoClock
Frequency
Multiplier x25
1
Output
Divider
2, 4, 5, 25
nQ0
Q1
nQ1
Q2
VCXO Jitter Attenuation PLL
nQ2
IDT
™
/ ICS
™
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
1
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4 , 23
5, 6
7,
9
8, 12, 17
10 ,
11
13
14
15
16,
18
19, 20
21, 22
Name
LF
V
CCA
V
CC
V
CCO
nQ0, Q0
PSEL0,
PSEL1
V
EE
XTAL_OUT,
XTAL_IN
nCLK
CLK
nBypass
FSEL1,
FSEL0
Q1, nQ1
Q2, nQ2
Type
Analog
Input/Output
Power
Power
Power
Output
Input
Power
Input
Input
Input
Input
Input
Output
Output
Pullup
Description
Loop filter connection node pin.
Analog supply pin.
Core power supply pin.
Output power supply pins.
Differential clock outputs. LVPECL interface levels.
Pre-divider select pins. See Table 3A.
Negative supply pins.
VCXO cr ystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Pullup/
Inver ting differential clock input. V
CC
/2 bias voltage when left floating.
Pulldown
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
PLL Bypass control pin. See Table 3D.
Select pins. See Table 3B.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Output enable. When logic LOW, the clock outputs are HiZ.
24
OE
Input
Pullup
When logic HIGH, the clock outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3C.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. P
RE
-
DIVIDER
F
UNCTION
T
ABLE
Inputs
PSEL1
0
0
1
1
PSEL0
0
1
0
1
Pre-divider Function
÷1
÷2.5
÷4
÷5
T
ABLE
3B. FSEL F
UNCTION
T
ABLE
Inputs
FSEL1
0
0
1
1
FSEL0
0
1
0
1
Output Divider
Function
÷2
÷4
÷5
÷25
IDT
™
/ ICS
™
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
2
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
T
ABLE
3C. OE F
UNCTION
T
ABLE
Input
OE
0
1
Clock Outputs
Q0:Q2
LOW
Enabled
nQ0:nQ2
HIGH
Enabled
T
ABLE
3D. B
YPASS
F
UNCTION
T
ABLE
nBypass Input
0
1 (default)
Normal operation mode.
Operation
VCXO jitter attenuation PLL and FemtoClock multiplier bypassed. Input passed directly to N divider.
T
ABLE
3E. F
REQUENCY
F
UNCTION
T
ABLE
Input
Frequency
(MHz)
25
25
25
25
62.5
62.5
62.5
62.5
100
100
100
100
100
100
100
100
125
125
125
125
Input
Divider
1
1
1
1
2.5
2.5
2.5
2.5
4
4
4
4
5
5
5
5
5
5
5
5
VCXO
Frequency
(MHz)
25
25
25
25
25
25
25
25
25
25
25
25
20
20
20
20
25
25
25
25
FemtoClock
Frequency
(MHz)
625
625
625
625
625
625
625
625
625
625
625
625
500
500
500
500
625
625
625
625
Output
Divider
2
4
5
25
2
4
5
25
2
4
5
25
2
4
5
25
2
4
5
25
Output
Frequency
(MHz)
312.5
156.25
125
25
312.5
156.25
125
25
312.5
156.25
125
25
250
125
100
20
312.5
156.25
125
25
PSEL1:0
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
11
11
11
11
FSEL1:0
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
IDT
™
/ ICS
™
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
3
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.12
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
132
12
19
Units
V
V
V
mA
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
=0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.12
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
CC
2.625
132
12
19
Units
V
V
V
mA
mA
mA
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
IDT
™
/ ICS
™
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
4
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
T
ABLE
4D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK, CLK
nCLK
CLK
Test Conditions
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, T
A
=0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
Parameter
Test Conditions
PSEL = ÷1
f
IN
Input Frequency
PSEL = ÷2.5
PSEL = ÷4
PSEL = ÷5
FSEL = ÷2
f
OUT
Output Frequency
FSEL = ÷4
FSEL = ÷5
FSEL = ÷25
156.25MHz, 25MHz cr ystal
Integration Range:
1.875MHz - 20MHz
20% to 80%
Minimum
19.6
49
78.4
98
245
122.5
98
19.6
0.37
400
8
1
48
800
40
3
60
52
Typical
Maximum
27.2
68
108.8
136
340
170
136
27.2
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
ms
t
jit(Ø)
t
R
/ t
F
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Cycle-to-Cycle Jitter ; NOTE 2, 3
Period Jitter ; NOTE 4
Output Skew; NOTE 3, 5
Output Duty Cycle
t
jit(cc)
t
jit(per)
t
sk(o)
odc
PLL Lock Time
t
LOCK
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Jitter performance using cr ystal inputs.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
IDT
™
/ ICS
™
JITTER ATTENUATOR/FREQUENCY TRANSLATOR
5
ICS813253AG REV. A JANUARY 5, 2007