MFC2000
Multifunctional Peripheral Controller 2000
Hardware Description
Doc. No. 100723A
June 21, 2000
Ordering Information
Marketing Name
Device Set Order No.
Part No.
MFC2000
xxx-xxx-xxx
xxxxx
Package
Part No.
Package
Revision History
Revision
A
A
Date
04/07/00
06/21/00
Comments
Initial, internal, preliminary release of document.
Second internal, preliminary release with revisions tracked.
© 2000, Conexant Systems, Inc. All Rights Reserved.
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Contents
1. INTRODUCTION .............................................................................................................................................. 1-1
1.1 SCOPE ...................................................................................................................................................... 1-1
1.2 SYSTEM OVERVIEW ................................................................................................................................ 1-1
1.3 REFERENCE DOCUMENTATION............................................................................................................ 1-5
2. MFC2000 SUMMARY ...................................................................................................................................... 2-1
2.1 MFC2000 DEVICE FAMILY....................................................................................................................... 2-1
2.2 MFC2000 SYSTEM BLOCK DIAGRAM .................................................................................................... 2-1
3. HARDWARE INTERFACE............................................................................................................................... 3-1
3.1 PIN DESCRIPTION ................................................................................................................................... 3-1
3.2 MAXIMUM RATINGS................................................................................................................................. 3-7
3.3 ELECTRICAL CHARACTERISTICS.......................................................................................................... 3-8
3.4 PIN LAYOUT............................................................................................................................................ 3-10
4. CPU AND BUS INTERFACE ........................................................................................................................... 4-1
4.1 MEMORY MAP AND CHIP SELECT DESCRIPTION ............................................................................... 4-1
4.2 CACHE MEMORY CONTROLLER.......................................................................................................... 4-19
4.3 SIU………. ............................................................................................................................................... 4-24
4.4 INTERRUPT CONTROLLER................................................................................................................... 4-46
4.5 DRAM CONTROLLER (INCLUDING BATTERY DRAM) ........................................................................ 4-54
4.6 FLASH MEMORY CONTROLLER........................................................................................................... 4-72
4.7 DMA CONTROLLER ............................................................................................................................... 4-76
5. RESET LOGIC/BATTERY BACKUP/WATCH DOG TIMER........................................................................... 5-1
5.1 RESET LOGIC/BATTERY BACKUP ......................................................................................................... 5-1
5.2 WATCHDOG TIMER ............................................................................................................................... 5-11
6. FAX TIMING CONTROL INTERFACE ............................................................................................................ 6-1
6.1 PLL………….. ............................................................................................................................................ 6-1
6.2 FAX TIMING LOGIC .................................................................................................................................. 6-2
6.3 MFC2000 TIMING CHAIN ......................................................................................................................... 6-3
6.4 SCAN CONTROL TIMING......................................................................................................................... 6-4
6.5 FAX TIMING REGISTERS......................................................................................................................... 6-5
7. VIDEO/SCANNER CONTROLLER ................................................................................................................. 7-1
7.1 SCANNER CONTROLLER........................................................................................................................ 7-2
7.2 SERIAL PROGRAMMING INTERFACE.................................................................................................. 7-41
7.3 VIDEO CONTROLLER ............................................................................................................................ 7-50
8. ADC……........................................................................................................................................................... 8-1
8.1 PADC AND SCAN ANALOG FRONT END ............................................................................................... 8-1
8.2 TADC……………………. ........................................................................................................................... 8-5
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9. BI-LEVEL RESOLUTION CONVERSION ....................................................................................................... 9-1
9.1 FUNCTIONAL DESCRIPTION .................................................................................................................. 9-1
9.2 REGISTER DESCRIPTION ....................................................................................................................... 9-6
9.3 RESOLUTION CONVERSION PROGRAMMING EXAMPLES............................................................... 9-15
10. EXTERNAL PRINT ASIC INTERFACE ......................................................................................................... 10-1
10.1
INTERFACE BETWEEN THE MFC2000 AND EXTERNAL PRINT ASIC .......................................... 10-1
11. BIT ROTATION LOGIC.................................................................................................................................. 11-1
11.1
11.2
11.3
11.4
FUNCTIONAL DESCRIPTION ............................................................................................................ 11-1
BLOCK DIAGRAM............................................................................................................................... 11-3
REGISTER DESCRIPTION................................................................................................................. 11-6
FIRMWARE OPERATION................................................................................................................. 11-10
12. PRINTER AND SCANNER STEPPER MOTOR INTERFACE ...................................................................... 12-1
12.1
12.2
VERTICAL PRINT STEPPER MOTOR INTERFACE ......................................................................... 12-1
SCANNER STEPPER MOTOR INTERFACE ..................................................................................... 12-5
13. GENERAL PURPOSE INPUTS/OUTPUTS (GPIO) ...................................................................................... 13-1
13.1
13.2
13.3
GPIO SIGNALS ................................................................................................................................... 13-1
GPO/GPI SIGNALS............................................................................................................................. 13-5
GPIO CONTROL AND DATA REGISTERS........................................................................................ 13-6
14. COMPRESSOR AND DECOMPRESSOR..................................................................................................... 14-1
14.1
14.2
FUNCTIONAL DESCRIPTION ............................................................................................................ 14-1
REGISTER DESCRIPTION................................................................................................................. 14-2
15. SYNCHRONOUS/ASYNCHRONOUS SERIAL INTERFACE (SASIF) ......................................................... 15-1
15.1
15.2
15.3
15.4
FUNCTIONAL DESCRIPTION ............................................................................................................ 15-1
REGISTER DESCRIPTION................................................................................................................. 15-3
SASIF TIMING................................................................................................................................... 15-12
FIRMWARE OPERATION................................................................................................................. 15-16
16. USB INTERFACE .......................................................................................................................................... 16-1
16.1
16.2
16.3
FUNCTION DESCRIPTION ................................................................................................................ 16-1
REGISTER DESCRIPTION................................................................................................................. 16-1
FIRMWARE OPERATION................................................................................................................. 16-23
17. BI-DIRECTIONAL PARALLEL PERIPHERAL INTERFACE........................................................................ 17-1
17.1
17.2
17.3
17.4
17.5
17.6
OPERATIONAL MODES..................................................................................................................... 17-1
ADDITIONAL FEATURES................................................................................................................... 17-2
FUNCTIONAL DESCRIPTION ............................................................................................................ 17-3
REGISTER DESCRIPTION................................................................................................................. 17-4
TIMING .............................................................................................................................................. 17-16
FIRMWARE OPERATION................................................................................................................. 17-22
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18. REAL-TIME CLOCK ...................................................................................................................................... 18-1
18.1
18.2
18.3
DESCRIPTION .................................................................................................................................... 18-1
REAL-TIME CLOCK (RTC) REGISTERS ........................................................................................... 18-2
RTC OPERATIONS............................................................................................................................. 18-3
19. SYNCHRONOUS SERIAL INTERFACE (SSIF)............................................................................................ 19-1
19.1
19.2
19.3
INTRODUCTION AND FEATURES .................................................................................................... 19-1
REGISTER DESCRIPTION................................................................................................................. 19-2
SSIF TIMING ....................................................................................................................................... 19-7
20. PROGRAMMABLE TONE GENERATORS .................................................................................................. 20-1
20.1
20.2
20.3
INTRODUCTION ................................................................................................................................. 20-1
BELL/RINGER GENERATOR ............................................................................................................. 20-1
TONE GENERATOR........................................................................................................................... 20-6
21. PWM LOGIC .................................................................................................................................................. 21-1
21.1
21.2
FUNCTIONAL DESCRIPTION ............................................................................................................ 21-1
REGISTER DESCRIPTION................................................................................................................. 21-2
22. CALLING PARTY CONTROL (CPC) ............................................................................................................ 22-1
22.1
REGISTERS DESCRIPTION .............................................................................................................. 22-5
23. SSD_P80 ........................................................................................................................................................ 23-1
23.1
23.2
23.3
FUNCTION DESCRIPTION ................................................................................................................ 23-1
REGISTER DESCRIPTION................................................................................................................. 23-3
FIRMWARE OPERATION................................................................................................................... 23-6
24. COUNTACH IMAGING DSP BUS SUBSYSTEM ......................................................................................... 24-1
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
COUNTACH IMAGING DSP SUBSYSTEM........................................................................................ 24-3
COUNTACH IMAGING DSP BUS UNIT ............................................................................................. 24-4
ARM BUS INTERFACE....................................................................................................................... 24-8
COUNTACH IMAGING DSP SUBSYSTEM INTERFACE ................................................................ 24-11
COUNTACH DMA CONTROLLER.................................................................................................... 24-12
VIDEO/SCANNER INTERFACE ....................................................................................................... 24-22
(S)DRAM CONTROLLER ((S)DRAMC) ............................................................................................ 24-23
REGISTER DESCRIPTION............................................................................................................... 24-28
25. CONFIGURATION ......................................................................................................................................... 25-1
25.1
25.2
HARDWARE VERSION ...................................................................................................................... 25-1
PRODUCT CODE ............................................................................................................................... 25-1
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