CD4019BPWE4 datasheet, PDF - EEWORLD Datasheet

CD4019BPWE4: DescriptionLogic Gates CMOS Quad AND/OR Select Gate; Categorylogic logic; File Size928KB，17 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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Logic Gates CMOS Quad AND/OR Select Gate

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Texas Instruments
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP16,.25
Contacts	16
Reach Compliance Code	unknown
Other features	CONFIGURABLE AS QUAD 2:1 MUX
series	4000/14000/40000
JESD-30 code	R-PDSO-G16
JESD-609 code	e4
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND-OR GATE
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	5/15 V
Prop。Delay @ Nom-Sup	300 ns
propagation delay (tpd)	300 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm

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