512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
Features
Synchronous DRAM Module
MT18LSDF6472 – 512MB
For the latest data sheet, refer to Micron’s Web site:
www.micron.com/products/modules
Features
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168-pin, dual in-line memory module (DIMM)
PC133-compliant
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
Utilizes 133 MHz SDRAM components
Supports ECC error detection and correction
512MB (64 Meg x 72)
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of PLL clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal SDRAM banks for hiding row access/
precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge
Auto refresh mode
Self refresh mode: 64ms, 8,192-cycle refresh
LVTTL-compatible inputs and outputs
Serial presence-detect (SPD)
Gold edge contacts
Timing Parameters
CL = CAS (READ) latency
Module
Marking
-13E
-133
Clock
Frequency
133 MHz
133 MHz
Access Time
CL = 2
5.4ns
–
CL = 3
–
5.4ns
Setup
Time
1.5
1.5
Hold
Time
0.8
0.8
Figure 1:
168-Pin DIMM (MO-161)
Standard 1.05in. (26.67mm)
Low-Profile 0.90in. (22.86mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS Latency
2
133 MHz/CL = 2
133 MHz/CL = 3
• PCB
Standard 1.05in. (26.67mm)
Low-Profile 0.9in. (22.86mm)
1
Marking
G
Y
1
-13E
-133
See note page 2
See note page 2
Table 1:
Notes:1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Table 2:
Parameter
Refresh count
Device banks
Device configuration
Row addressing
Column addressing
Module ranks
Address Table
512MB
8K
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
2K (A0–A9, A11)
1 (S0#, S2#)
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
Features
Table 3:
Part Numbers
Module Density
512MB
512MB
512MB
512MB
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
System Bus Speed
133 MHz
133 MHz
133 MHz
133 MHz
Part Number
MT18LSDF6472G-13E__
MT18LSDF6472Y-13E__
MT18LSDF6472G-133__
MT18LSDF6472Y-133__
Notes: 1. The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT18LSDF6472G-133B1.
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
168-Pin DIMM Front
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
WP
SDA
SCL
V
DD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
168-Pin DIMM Back
106
CB5
127
V
SS
148
107
V
SS
128
CKE0
149
108
NC
129
NC
150
109
NC
130 DQMB6
151
110
V
DD
131 DQMB7 152
111
CAS#
132
NC
153
112 DQMB4 133
V
DD
154
113 DQMB5 134
NC
155
114
NC
135
NC
156
115
RAS#
136
CB6
157
116
V
SS
137
CB7
158
117
A1
138
V
SS
159
118
A3
139 DQ48 160
119
A5
140 DQ49 161
120
A7
141 DQ50
162
121
A9
142 DQ51
163
122
BA0
143
V
DD
164
123
A11
144 DQ52
165
124
V
DD
145
NC
166
125
NC
146
NC
167
126
A12
147
REGE
168
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
DD
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Figure 2:
168-Pin DIMM Pin Locations
Low-Profile 0.90in. (22.86mm)
U7
U8
U9
U10
U1
U2
U3
U4
U5
U11
Standard 1.05in. (26.67mm)
U1
U2
U3
U4
U7
U6
U8
U9
U10
U5
U6
U11
PIN 1
PIN 41
PIN 84
PIN 1
PIN 41
PIN 84
U17
U12
U13
U14
U15
U16
U20
U21
U22
U23
U24
U12
U13
U14
U15
U16
U17
U20
U21
U22
U23
U24
U19
U19
PIN 168
PIN125
PIN 85
PIN 168
PIN125
PIN 85
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Pins
27, 111, 115
42
128
Pin Descriptions
Pin numbers not listed in correct order; for more information, see Pin Assignment tables on page 3
Symbol
WE#, CAS#,
RAS#
CK0
CKE0
Type
Input
Input
Input
Description
Command inputs: WE#, CAS#, and RAS# (along with S#) define the
command being entered.
Clock: CK is distributed through an on-board PLL to all devices.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH
operation (all device banks idle) or CLOCK SUSPEND operation (burst
access in progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including CKE, are
disabled during power-down and self refresh modes, providing low
standby power.
Chip select: S# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.
Input/Output mask: DQMB is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQMB is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH
during a READ cycle.
Bank address: BA0 and BA1 define to which device bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE REGISTER
SET command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to configure the
presence-detect device.
Register enable.
Data I/Os: Data bus.
30, 45
S0#, S2#
Input
28, 29, 46, 47, 112,
113, 130, 131
DQMB0–
DQMB7
Input
39, 122
33–38, 117–121, 123,
126
BA0, BA1
A0–A12
Input
Input
83
166, 167, 168
147
2–5, 7–11, 13–17, 19,
20, 55–58, 60, 65–67,
69–82, 74–77, 86–89,
91–95, 97–101, 103,
104, 139–142, 144,
149–151, 153–156,
158–161
21, 22, 52, 53, 105,
106, 136, 137
82
SCL
SA0–SA2
REGE
DQ0–DQ63
Input
Input
Input
Input/
Output
CB0–CB7
SDA
Input/
Output
Input/
Output
ECC check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of
the module.
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
Functional Block Diagram
Table 5:
Pins
6, 18, 26, 40, 41, 49,
59, 72, 84, 90, 102,
110, 124, 133, 143,
157, 168
1, 12, 23, 32, 43, 54,
64, 68, 78, 85, 96,
107, 116, 127, 138,
148, 152, 162
24, 25, 31, 44, 48, 50,
51, 61, 62, 63, 79, 80,
81, 108, 109, 114,
125, 129, 132, 134,
135, 145, 146, 163,
164
Pin Descriptions
Pin numbers not listed in correct order; for more information, see Pin Assignment tables on page 3
Symbol
V
DD
Type
Supply
Description
Power supply: +3.3V ±0.3V.
V
SS
Supply
Ground.
NC
–
Not connected: These pins are not connected on this module.
Functional Block Diagram
Per industry standard, Micron modules utilize various component speed grades, as ref-
erenced in the module part number guide at
www.micron.com/support/number-
ing.html.
Standard modules use the following SDRAM devices: MT48LC64M4A2FB (512MB).
Lead-free modules use the following SDRAM devices: MT48LC64M4A2BB (512MB).
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
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