.
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
Features
• 168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
• Intended for PC100 applications
• Clock Frequency: 100MHz
• Clock Cycle: 10.0ns
• -260 and -360 speed sorts
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V
±
0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have four internal banks
• Module has one physical bank
• Fully Synchronous to positive Clock Edge
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge commands
• Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page
(Full-Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Suspend Mode and Power Down Mode
• 12/10/2 Addressing (Row/Column/Bank)
• 4096 Refresh cycles distributed across 64ms
• Card size: 5.25" x 1.375" x 0.106"
• Gold contacts
• SDRAMs in TSOP Type II Package
• Serial Presence Detect with Write Protect
Description
IBM13N16644JCA / IBM13N16734JCA are unbuf-
fered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
16Mx64 and 16Mx72 high-speed memory arrays
and are configured as one 16M x 64/72 physical
bank. The DIMMs use eight (16Mx64) or nine
(16Mx72) 16Mx8 SDRAMs in 400mil TSOP II pack-
ages. The DIMMs achieve high-speed data transfer
rates of up to 100MHz by employing a prefetch/pipe-
line hybrid architecture that supports the JEDEC 1N
rule while allowing very low burst power.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK2). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0/S2, DQMB, and CKE0 signals. A
command decoder initiates the necessary timings
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and Burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
Card Outline
(Front)
(Back)
1
85
10 11
94 95
40 41
124 125
84
168
06K3912.H01723
1/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 18
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
Pin Description
CK0, CK2
CK1, CK3
CKE0
RAS
CAS
WE
S0, S2
A0 - A9, A11
A10 /AP
BA0, BA1
Clock Inputs
Unused (terminated) Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
DQ0 - DQ63
CB0 - CB7
DQMB0 - DQMB7
V
DD
V
SS
NC
SCL
SDA
SA0-2
WP
Data Input/Output
Check Bit Data Input/Output
Data Mask
Power (3.3V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data Input/Output
Serial Presence Detect Address Inputs
Serial Presence Detect Write Protect Input
Pinout
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Front
Side
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
Pin#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Back
Side
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
Pin#
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Front
Side
CB1
V
SS
NC
NC
V
DD
WE
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CK0
Pin#
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Back
Side
CB5
V
SS
NC
NC
V
DD
CAS
DQMB4
DQMB5
NC
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CK1
NC
Pin#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Front
Side
V
SS
NC
S2
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
Pin#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Back
Side
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
Pin#
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
Side
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
Pin#
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
Side
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
*CK3
NC
SA0
SA1
SA2
V
DD
Note:
All pin assignments are consistent for all 8-byte unbuffered versions. Check bits (CB0 - CB7) are applicable only to the x72 DIMM; for the x64 DIMM
these pins are no connects (NC). *CK1 and CK3 are terminated.
Ordering Information
Part Number
IBM13N16644JCA-260T
IBM13N16644JCA-360T
IBM13N16734JCA-260T
IBM13N16734JCA-360T
Organization
16Mx64
16Mx64
16Mx72
16Mx72
Clock Cycle
Leads
Dimension
Power
10.0ns
Gold
5.25
"
x 1.375
"
x 0.106
"
3.3V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K3912.H01723
1/00
Page 2 of 18
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
16Mx64 SDRAM DIMM Block Diagram
(1 Bank, 16Mx8 SDRAMs)
S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
*
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
D4
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D1
D5
S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D2
D6
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB7
D3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
Note: Exact DQ wiring may differ from that shown above.
10 Ohm
CK1
BA0
10pF
CK3
10 Ohm
BA1
CK0
CK2
V
DD
.33µF
V
SS
D0 - D7
0.1µF
D0 - D7
RAS
CAS
CKE0
WE
* All resistor values are 10 ohms except as shown.
A12/BS1: SDRAMs D0 - D7
CLK: SDRAMs D0 - D1, D4 - D5, 3.3pF Cap.
CLK: SDRAMs D2 - D3, D6 - D7, 3.3pF Cap.
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
SCL
WP
47K
SA0
SA1
SA2
Serial PD
SDA
A0
A1
A2
A13/BS0: SDRAMs D0 - D7
10pF
A0 - A11
A0-A11: SDRAMs D0 - D7
06K3912.H01723
1/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 18
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
16Mx72 SDRAM DIMM Block Diagram
S0
DQMB0
*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
(1 Bank, 16Mx8 SDRAMs)
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
D5
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D1
D6
DQMB6
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
D3
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
Note: Exact DQ wiring may differ from that shown above.
CK1
A0 - A11
BA0
BA1
CK0
CK2
A0-A11: SDRAMs D0 - D8
A13/BS0: SDRAMs D0 - D8
A12/BS1: SDRAMs D0 - D8
CLK: SDRAMs D0 - D2, D5 - D6
CLK: SDRAMs D3 - D4, D7 - D8, 3.3pF Cap.
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
CKE: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
SCL
WP
47K
10 Ohm 10pF
10pF
CK3
10 Ohm
D4
V
DD
.33µF
V
SS
D0 - D8
0.1µF
D0 - D8
RAS
CAS
CKE0
WE
Serial PD
SDA
A0
SA0
A1
SA1
A2
SA2
* All resistor values are 10 ohms except as shown.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
06K3912.H01723
1/00
Page 4 of 18
IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
Input/Output Functional Description
Symbol
CK0, CK2
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Active
High
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
Activates the CK0 and CK2 signals when high and deactivates them when low. By deac-
tivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CKE0
Input
Level
S0,S2
RAS, CAS
WE
BA0, BA1
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the command
Active Low decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 define the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all four banks will be precharged regardless of
the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the Write operation
if DQM is high.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
Power and ground for the module.
Input
Input
Pulse
Level
A0 - A9
A10/AP
A11
Input
Level
—
DQ0 - DQ63, Input
CB0 - CB7
Output
Level
—
DQMB0 -
DQMB7
Input
Pulse
Active
High
SA0 - SA2
Input
Level
—
SDA
Input
Output
Level
—
SCL
Input
Pulse
—
WP
V
DD
, V
SS
Input
Level
Active
High
Supply
06K3912.H01723
1/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 18