............................ Dependent on External FET
XTR Supply Voltage, External V
S
(Referenced to I
RET
Pin) ............ +5.5V
Input Voltage to Multiplexer (Referenced to I
RET
Pin) ................ 0V to V
S
Output Current Limit ................................................................ Continuous
Storage Temperature Range ......................................... –55°C to +125°C
Junction Temperature .................................................................... +165°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
(1)
PACKAGE
DESIGNATOR
DBQ
SPECIFIED
TEMPERATURE
RANGE
–40°C to +85°C
PACKAGE
MARKING
XTR108EA
ORDERING
NUMBER
XTR108EA
XTR108EA/2K5
TRANSPORT
MEDIA, QUANTITY
Rails
Tape and Reel, 2500
PRODUCT
XTR108EA
PACKAGE-LEAD
SSOP-24
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ELECTRICAL CHARACTERISTICS
Boldface
limits apply over the specified temperature range,
T
A
= –40
°
C to +85
°
C.
At T
A
= +25°C, V
PS
= 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to I
RET
pin.
XTR108EA
PARAMETER
V
IN
TO I
OUT
TRANSFER FUNCTION
Output
Specified Range
Over-Scale Limit Resolution
Fault Over-Scale Level
(1)
Under-Scale Limit Resolution
Fault Under-Scale Level
(1)
Output for Zero Input
Zero Error, Unadjusted
vs Temperature
vs Loop-Supply Voltage, V
LOOP
vs Common-Mode Voltage
Adjustment Resolution, Zero Input
Adjustment Range, Zero Input
Span
(2)
Initial, Unadjusted
Drift (vs Temperature)
Span Adjustment Resolution
Span Adjustment Range
PGA + Output Amplifier
(3)
Nonlinearity, Ideal Input
PGA
Autozeroing Internal Frequency
PGA Offset Voltage (RTI)
(4)
vs Temperature
vs Supply Voltage, V
S
vs Common-Mode Voltage
Common-Mode Input Range
Input Bias Current
vs Temperature
Input Offset Current
vs Temperature
CONDITIONS
I
O
= V
IN
(Span) + 4mA
4
Digital Select: 21-28.5mA
Above Over-Scale Selected
Digital Select: 2.2-3.6mA
Below Under-Scale Selected
V
IN
= 0V
V
LOOP
= 7.5V to 24V
V
CM
= 0.2V to 3.5V
0.5
+1.0
0.2
–0.4
±50
±0.2
0.02
±1
1.8
±4
±1
40
0.05
49.3
0.01
6.5
±10
±0.02
±0.5
105
0.2
50
Doubles/10°C
10
Doubles/10°C
3150
20
mA
mA
mA
mA
mA
µA
µA/°C
µA/V
µA/V
µA/Step
mA
%
ppm/°C
%
mA/V
%
kHz
µV
µV/°C
µV/V
dB
V
pA
pA
pA
pA
MIN
TYP
MAX
UNITS
±1.5
Span = I
O
/V
IN
R
VI
= 6.34kΩ
Full-Scale V
IN
= 50mV
V
CM
= 1V
V
S
= 4.5V to 5.5V
V
CM
= 0.2V to 3.5V
±50
V
S
– 1.5
2
XTR108
www.ti.com
SBOS187B
ELECTRICAL CHARACTERISTICS
(Cont.)
Boldface
limits apply over the specified temperature range,
T
A
= –40
°
C to +85
°
C.
At T
A
= +25°C, V
PS
= 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to I
RET
pin.
XTR108EA
PARAMETER
PGA (Cont.)
Input Impedance: Differential
Input Impedance: Common-Mode
Voltage Noise, 0.1Hz to 10Hz
PGA Gain
Gain Range Steps
Initial Error
CONDITIONS
MIN
TYP
30 || 6
50 || 20
6
6.25, 12.5, 25, 50, 100, 200, 400
Gain = 6.25, 12.5, 25, 50
G = 100, 200
G = 400
R
LOAD
= 6.34kΩ to I
RET
for 4-20mA XTR Output
6.25
±0.5
±0.5
±0.8
±30
0.2
0.5 to 2.5
200
+6/–9
400
±2.5
±3
±3.5
4.5
MAX
UNITS
GΩ || pF
GΩ || pF
µVp-p
V/V
%
%
%
ppm/°C
V
V
pF
mA
vs Temperature
Output Voltage Range
(5)
Typical Operating Range
Capacitive Drive
Short-Circuit Current
ZERO OFFSET DACS
Zero-Code Output Level
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Coarse DAC, 256 Steps
Adjustment Range
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Step Size
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Linearity
Fine DAC, 256 Steps
Adjustment Range
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Step Size
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Linearity
Noise, RTO
(6)
CURRENT AMPLIFIER
Current Gain
Current Gain Drift
CURRENT SOURCES, I
REF1
AND I
REF2
Zero-Code Output Level, Each
Coarse DAC, 256 Steps
Adjustment Range
(7)
Step Size
Fine DAC, 256 Steps
Adjustment Range
(7)
Step Size
Linearity
Coarse
Fine
vs Temperature
Matching
vs Temperature
Compliance Voltage, Positive
(5)
Output Impedance
Current Noise
LINEARIZATION DAC
Linearization Range, 256 Steps
Max Linearization Coefficient
Step Size
SUB REGULATOR, V
S
Voltage
vs Temperature
vs Loop-Supply Voltage
V
CM
= 1V, V
IN
= 0V
R
V/I
= 6.34kΩ
4.116
522
7 Bits + Sign
–3.77 to +3.77
–470 to +470
0.029
3.7
±0.5
7 Bits + Sign
–236 to +236
–29.4 to +29.4
0.0018
0.23
±1
1.1
49
50
10
493
7 Bits + Sign
–195 to +195
1.54
7 Bits + Sign
–12.2 to +12.2
96
±0.2
±0.5
±35
±0.2
±10
V
S
– 1.5
100
0.015
8 Bits
0.99
3.9
4.8
5.1
±50
±0.03
5.4
51
mA
mV
Relative to Zero-Code Level
mA
mV
mA
mV
LSB
Relative to Zero-Code Level
µA
mV
mA
mV
LSB
µAp-p
A/A
ppm/°C
µA
µA
µA
µA
nA
LSB
LSB
ppm/°C
%
ppm/°C
V
MΩ
µAp-p
f = 0.1Hz to 10Hz
R
SET
= 12.1kΩ
480
510
V
S
– 2
f = 0.1Hz to 10Hz
∆I
REF
/∆V
IN
, R
LIN
= 15.8kΩ
Supply Voltage for XTR
µA/mV
nA/mV
V
ppm/°C
mV/V
V
LOOP
= 7.5V to 24V
XTR108
SBOS187B
www.ti.com
3
ELECTRICAL CHARACTERISTICS
(Cont.)
Boldface
limits apply over the specified temperature range,
T
A
= –40
°
C to +85
°
C.
At T
A
= +25°C, V
PS
= 24V, and Supertex DN2540 external depletion-mode FET transistor, unless otherwise noted, all voltages measured with respect to I
RET
pin.
XTR108EA
PARAMETER
OVER- AND UNDER-SCALE LIMITING
Over-Scale DAC: 16 Steps
Adjustment Range
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Step Size
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Accuracy
Under-Scale DAC: 8 Steps
Adjustment Range
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Step Size
RTO
(6)
of Current Amplifier
RTO
(6)
of PGA
Accuracy
VOLTAGE REFERENCE, V
REF
Internal Bandgap
vs Temperature
UNCOMMITTED OP AMP
Input
Offset Voltage
vs Temperature
vs Common-Mode Voltage
Open-Loop Gain
Common-Mode Input Range
Output Voltage Range
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
V
IL
V
IH
V
OL
V
OH
Input Current
I
IH
(CS1)
I
IL
(CS1)
I
IH
, I
IL
(SCLK, DIO)
INTERNAL OSCILLATOR
Frequency, f
OSC
TEMPERATURE RANGE
Specification
Operating
θ
JA
, Junction to Ambient
LOOP SUPPLY
Voltage Range
Quiescent Current
with Supertex DN2540
R
SET
Open, L
IN
Reg = 0, No Sensor Current
(8)(9)
–40
–55
100
7.5
0.5
CONDITIONS
MIN
TYP
4
R
VI
= 6.34kΩ
20.7 to 28.1
2.625 to 3.563
0.49
62.5
±10
3
R
VI
= 6.34kΩ
2.17 to 3.55
275 to 450
0.195
25
±5
1.193
±5
MAX
UNITS
Bits
mA
V
mA
mV
%
Bits
mA
mV
mA
mV
%
V
ppm/°C
±50
V
CM
= 2V
±2
±3
90
110
0 to 3.5
0.2
CMOS
0
3.5
0.8
V
S
0.4
V
S
– 0.2
R
L
= 10kΩ to V
S
/ 2
mV
µV/°C
dB
dB
V
V
I
OL
= 300µA
I
OH
= –300µA
3.5 < V
IN
< V
S
0 < V
IN
< 0.8
0 < V
IN
< V
S
V
S
– 1
–200
–20
–20
–120
–6
–6
210
+85
+125
10
10
10
V
V
V
V
µA
µA
µA
kHz
°C
°C
°C/W
V
mA
NOTES: (1) Over-scale and under-scale complies with NAMUR NE43 recommendation. (2) Span adjustment is determined by PGA gain and sensor
excitation. (3) Span can be digitally adjusted in three ways: PGA gain, current reference Coarse, and current reference Fine. (4) RTI = Referred to Input.
(5) Current source output voltage measured with respect to I
RET
. (6) RTO = Referred to Output. (7) Excitation DAC range sufficient to adjust span fully
between PGA gain steps. (8) Output current into external circuitry is limited by an external MOS power FET. (9) Measured with over- and under-scale limits
disabled.
4
XTR108
www.ti.com
SBOS187B
PIN CONFIGURATION
Top View
SSOP
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
C
FILTER
R
LIN
V
O
I
IN
I
O
I
RET
1
2
3
4
5
6
XTR108
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OPA +IN
OPA –IN
OPA OUT
REF
OUT
REF
IN
R
SET
CS1
SCLK
SDIO
CS2
V
GATE
V
S
PIN ASSIGNMENTS
PIN
V/I-0
V/I-1
V/I-2
V/I-3
V/I-4
V/I-5
C
FILTER
R
LIN
V
O
I
IN
I
O
I
RET
V
S
V
GATE
CS2
SDIO
SCLK
CS1
R
SET
REF
IN
REF
OUT
OPA OUT
OPA –IN
OPA +IN
MUX
MUX
MUX
MUX
MUX
MUX
Input
Input
Input
Input
Input
Input
NAME
Channel 0 and/or I
REF
Out
Channel 1 and/or I
REF
Out
Channel 2 and/or I
REF
Out
Channel 3 and/or I
REF
Out
Channel 4 and/or I
REF
Out
Channel 5 and/or I
REF
Out
Filter Capacitor
Linearization
PGA Output
Current Input
Output Current
Return Current
Voltage Regulator
Gate Voltage
Chip Select 2
Serial Data Input/Output
Serial Clock
Chip Select 1
Resistor for Reference
Voltage Reference Input
Voltage Reference Output
Uncommitted Op Amp Output
Uncommitted Op Amp Negative Input
Uncommitted Op Amp Positive Input
FUNCTION
MUX Input to PGA and/or I
REF
to Sensor
MUX Input to PGA and/or I
REF
to Sensor
MUX Input to PGA and/or I
REF
to Sensor
MUX Input to PGA and/or I
REF
to Sensor
MUX Input to PGA and/or I
REF
to Sensor
MUX Input to PGA and/or I
REF
to Sensor
Filter to Reduce Chopper Noise in Autozeroing PGA
Linearization Range Adjustment Resistor
PGA Amplified Output of Differential Sensor Input
Input to Output Current Amplifier
4-20mA Current for Output Loop
Return for All External Circuitry Current
Supply Voltage for XTR and External Circuitry, If Used
Gate Voltage for External MOSFET Transistor
Select for XTR Serial Port to External EEPROM (Output from XTR Only)
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