PIC17C42-25I/P datasheet, PDF - EEWORLD Datasheet

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PIC17C42-25I/P: Description8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size59KB，4 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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PIC17C42-25I/P Overview

8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44

PIC17C42-25I/P Parametric

Parameter Name	Attribute value
Maker	Microchip
Parts packaging code	DIP
package instruction	0.600 INCH, PLASTIC, DIP-40
Contacts	40
Reach Compliance Code	unknow
Has ADC	NO
Address bus width	16
bit size	8
CPU series	PIC
maximum clock frequency	25 MHz
DAC channel	NO
DMA channel	NO
External data bus width	16
JESD-30 code	R-PDIP-T40
length	51.689 mm
Number of I/O lines	33
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	232
rom(word)	2048
ROM programmability	OTPROM
Maximum seat height	5.08 mm
speed	25 MHz
Maximum slew rate	38 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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PIC17C44

PIC17C44 Rev. A Silicon Errata Sheet

The PIC17C44 (Rev. A) parts you have received con-

form functionally to the PIC17C4X preliminary data

sheet (DS30412

), except for the following clariﬁca-

tions and corrections.

NONE

Clariﬁcations/Corrections to the Data Sheet:

The PIC17C44 Preliminary Data Sheet (document

DS30412

) that you have received, requires the follow-

ing clariﬁcations and corrections.

The clearing of any interrupt enable bit(s) in the

INTSTA register should be preceded by the dis-

abling of the global interrupt control bit (setting

GLINTD). Global interrupts may then be re-

enabled. The individual interrupts may be re-

enabled without further control of the GLINTD

bit.

When global interrupts are enabled, if the interrupt

ﬂag is being set when the corresponding enable bit

is being cleared the device will branch to the reset

vector address (0h). The interrupt ﬂag will not be

(automatically) cleared.

The

RETURN

instruction causes an update of the

PCLATH register. The PCLATH register is

loaded with the high address of the

RETURN

instruction.

The Table write to internal program memory (self

programming) can occur even when the MCLR

pin is either at the V

or V

IHH

voltage level.

When the MCLR pin is at V

, the table write

sequence occurs, but the programming voltage

is marginal since the MCLR pin is not at the cor-

rect level. This table write may cause the speci-

ﬁed program memory location to be corrupted

(depending on the data in the TABLAT register).

Note:

As with any windowed EPROM device, please cover the window at all times, except when erasing.

October, 1997 Microchip Technology Inc.

DS30412C/44/E1A2-page 1

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