Parity Generator/Checker, 4000/14000/40000 Series, 9-Bit, Complementary Output, CMOS, CDIP14
Parameter Name | Attribute value |
package instruction | , |
Reach Compliance Code | unknown |
Other features | ODD/EVEN PARITY GENERATOR; WITH INHIBIT |
series | 4000/14000/40000 |
JESD-30 code | R-CDIP-T14 |
Logic integrated circuit type | PARITY GENERATOR/CHECKER |
Number of digits | 9 |
Number of functions | 1 |
Number of terminals | 14 |
Maximum operating temperature | 125 °C |
Minimum operating temperature | -55 °C |
Output polarity | COMPLEMENTARY |
Package body material | CERAMIC, METAL-SEALED COFIRED |
Package shape | RECTANGULAR |
Package form | IN-LINE |
propagation delay (tpd) | 945 ns |
Certification status | Not Qualified |
Maximum supply voltage (Vsup) | 18 V |
Minimum supply voltage (Vsup) | 3 V |
Nominal supply voltage (Vsup) | 5 V |
surface mount | NO |
technology | CMOS |
Temperature level | MILITARY |
Terminal form | THROUGH-HOLE |
Terminal location | DUAL |
total dose | 100k Rad(Si) V |
Base Number Matches | 1 |