MT48LC16M16A2P-6A L:G TR datasheet, PDF

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MT48LC16M16A2P-6A L:G TR: DescriptionIC sdram 256mbit 167mhz tsop; Categorystorage; File Size1MB，87 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT48LC16M16A2P-6A L:G TR Overview

IC sdram 256mbit 167mhz tsop

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256Mb: x4, x8, x16 Automotive SDRAM

Features

Automotive SDR SDRAM

MT48LC64M4A2 – 16 Meg x 4 x 4 banks

MT48LC32M8A2 – 8 Meg x 8 x 4 banks

MT48LC16M16A2 – 4 Meg x 16 x 4 banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AAT devices)

• Auto refresh

– 64ms, 8192-cycle (commercial and industrial)

– 16ms, 8192-cycle (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• AEC-Q100

• PPAP submission

• 8D response time

Options

– 54-pin TSOP II OCPL

(400 mil)

Pb-free

– 60-ball FBGA (x4, x8) (8mm x 16mm)

Pb-free

– 54-ball VFBGA (x16) (8mm x 14 mm)

Pb-free

– 54-ball VFBGA (x16) (8mm x 8 mm)

Pb-free

Timing – cycle time

– 6ns @ CL = 3 (x8, x16 only)

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

Self refresh

– Standard

– Low power

Operating temperature range

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

Revision

Notes:

Off-center parting line.

Only available on Revision D.

Only available on Revision G.

Contact Micron for availability.

Marking

•

-6A

-75

-7E

None

AIT

AAT

:D/:G

•

Options

• Configurations

– 64 Meg x 4 (16 Meg x 4 x 4 banks)

– 32 Meg x 8 (8 Meg x 8 x 4 banks)

– 16 Meg x 16 (4 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

• Plastic package – OCPL

– 54-pin TSOP II OCPL

(400 mil)

(standard)

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-7E

-75

-7E

-75

Clock

Frequency

167 MHz

143 MHz

133 MHz

100 MHz

Marking

64M4

32M8

16M16

•

Access Time

CL = 2

–

5.4ns

6ns

CL = 3

5.4ns

–

Setup Time

1.5ns

Hold Time

0.8ns

PDF: 09005aef848d99e8

256Mb_ait_aat_sdr_esg.pdf - Rev. C 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

256Mb: x4, x8, x16 Automotive SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ..................................................................................................... 11

Package Dimensions ....................................................................................................................................... 15

Temperature and Thermal Impedance ............................................................................................................ 19

Electrical Specifications .................................................................................................................................. 23

Electrical Specifications – I

Parameters ........................................................................................................ 25

Electrical Specifications – AC Operating Conditions ......................................................................................... 27

Functional Description ................................................................................................................................... 30

Commands .................................................................................................................................................... 31

COMMAND INHIBIT .................................................................................................................................. 31

NO OPERATION (NOP) ............................................................................................................................... 32

LOAD MODE REGISTER (LMR) ................................................................................................................... 32

ACTIVE ...................................................................................................................................................... 32

READ ......................................................................................................................................................... 33

WRITE ....................................................................................................................................................... 34

PRECHARGE .............................................................................................................................................. 35

BURST TERMINATE ................................................................................................................................... 35

AUTO REFRESH ......................................................................................................................................... 36

SELF REFRESH ........................................................................................................................................... 36

Truth Tables ................................................................................................................................................... 37

Initialization .................................................................................................................................................. 42

Mode Register ................................................................................................................................................ 44

Burst Length .............................................................................................................................................. 46

Burst Type .................................................................................................................................................. 46

CAS Latency ............................................................................................................................................... 48

Operating Mode ......................................................................................................................................... 48

Write Burst Mode ....................................................................................................................................... 48

Bank/Row Activation ...................................................................................................................................... 49

READ Operation ............................................................................................................................................. 50

WRITE Operation ........................................................................................................................................... 59

Burst Read/Single Write .............................................................................................................................. 66

PRECHARGE Operation .................................................................................................................................. 67

Auto Precharge ........................................................................................................................................... 67

AUTO REFRESH Operation ............................................................................................................................. 79

SELF REFRESH Operation ............................................................................................................................... 81

Power-Down .................................................................................................................................................. 83

Clock Suspend ............................................................................................................................................... 84

Revision History ............................................................................................................................................. 87

Rev. C – 1/14 ............................................................................................................................................... 87

Rev. B – 11/13 ............................................................................................................................................. 87

Rev. A – 04/12 ............................................................................................................................................. 87

PDF: 09005aef848d99e8

256Mb_ait_aat_sdr_esg.pdf - Rev. C 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb: x4, x8, x16 Automotive SDRAM

Features

List of Figures

Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 32 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 15

Figure 8: 60-Ball TFBGA "FB/BB" (8mm x 16mm) (x4, x8) ............................................................................... 16

Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 17

Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 18

Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21

Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22

Figure 14: ACTIVE Command ........................................................................................................................ 32

Figure 15: READ Command ........................................................................................................................... 33

Figure 16: WRITE Command ......................................................................................................................... 34

Figure 17: PRECHARGE Command ................................................................................................................ 35

Figure 18: Initialize and Load Mode Register .................................................................................................. 43

Figure 19: Mode Register Definition ............................................................................................................... 45

Figure 20: CAS Latency .................................................................................................................................. 48

Figure 21: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 49

Figure 22: Consecutive READ Bursts .............................................................................................................. 51

Figure 23: Random READ Accesses ................................................................................................................ 52

Figure 24: READ-to-WRITE ............................................................................................................................ 53

Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54

Figure 26: READ-to-PRECHARGE .................................................................................................................. 54

Figure 27: Terminating a READ Burst ............................................................................................................. 55

Figure 28: Alternating Bank Read Accesses ..................................................................................................... 56

Figure 29: READ Continuous Page Burst ......................................................................................................... 57

Figure 30: READ – DQM Operation ................................................................................................................ 58

Figure 31: WRITE Burst ................................................................................................................................. 59

Figure 32: WRITE-to-WRITE .......................................................................................................................... 60

Figure 33: Random WRITE Cycles .................................................................................................................. 61

Figure 34: WRITE-to-READ ............................................................................................................................ 61

Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 62

Figure 36: Terminating a WRITE Burst ............................................................................................................ 63

Figure 37: Alternating Bank Write Accesses ..................................................................................................... 64

Figure 38: WRITE – Continuous Page Burst ..................................................................................................... 65

Figure 39: WRITE – DQM Operation ............................................................................................................... 66

Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 68

Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69

Figure 42: READ With Auto Precharge ............................................................................................................ 70

Figure 43: READ Without Auto Precharge ....................................................................................................... 71

Figure 44: Single READ With Auto Precharge .................................................................................................. 72

Figure 45: Single READ Without Auto Precharge ............................................................................................. 73

Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74

Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74

Figure 48: WRITE With Auto Precharge ........................................................................................................... 75

Figure 49: WRITE Without Auto Precharge ..................................................................................................... 76

Figure 50: Single WRITE With Auto Precharge ................................................................................................. 77

PDF: 09005aef848d99e8

256Mb_ait_aat_sdr_esg.pdf - Rev. C 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT48LC16M16A2P-6A L:G TR Related Products

	MT48LC16M16A2P-6A L:G TR	MT48LC16M16A2B4-7E:G TR	MT48LC16M16A2B4-7E:G	MT48LC16M16A2P-6A L:G
Description	IC sdram 256mbit 167mhz tsop	IC sdram 256mbit 133mhz vfbga	IC sdram 256mbit 133mhz vfbga	IC sdram 256mbit 167mhz tsop

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