M93C86, M93C76, M93C66
M93C56, M93C46, M93C06
16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide)
MICROWIRE Serial Access EEPROM
FEATURES SUMMARY
s
Industry Standard MICROWIRE Bus
s
Figure 1. Packages
Single Supply Voltage:
– 4.5V to 5.5V for M93Cx6
– 2.5V to 5.5V for M93Cx6-W
– 1.8V to 5.5V for M93Cx6-R
8
1
PDIP8 (BN)
s
s
Dual Organization: by Word (x16) or Byte (x8)
Programming Instructions that work on: Byte,
Word or Entire Memory
Self-timed Programming Cycle with Auto-Erase
Ready/Busy Signal During Programming
Speed:
– 1MHz Clock Rate, 10ms Write Time (Current
product, identified by process identification
letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process identification
letter W)
s
s
s
8
1
SO8 (MN)
150 mil width
s
s
s
s
Sequential Read Operation
Enhanced ESD/Latch-Up Behaviour
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
TSSOP8 (DS)
3x3mm body size
TSSOP8 (DW)
169 mil width
M93C06 IS “NOT FOR NEW DESIGN”
The M93C06 is still in production, but is not recom-
mended for new designs. Please refer to AN1571
on how to replace the M93C06 by the M93C46 in
your application.
March 2003
1/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed through a Se-
rial Data Input (D) and Serial Data Output (Q)
using the MICROWIRE bus protocol.
Figure 2. Logic Diagram
Table 2. Memory Size versus Organization
Device
Number
of Bits
16384
8192
4096
2048
1024
256
Number
of 8-bit
Bytes
2048
1024
512
256
128
32
Number
of 16-bit
Words
1024
512
256
128
64
16
M93C86
M93C76
M93C66
VCC
M93C56
M93C46
D
C
M93Cx6
S
ORG
Q
M93C06
1
Note: 1. Not for New Design
The M93Cx6 is accessed by a set of instructions,
as summarized in Table 3, and in more detail in
Table 4 to Table 6).
Table 3. Instruction Set for the M93Cx6
VSS
AI01928
Instruction
READ
WRITE
EWEN
EWDS
ERASE
Description
Read Data from Memory
Write Data to Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
Write All Memory
with same Data
Data
Byte or Word
Byte or Word
Byte or Word
Table 1. Signal Names
S
D
Q
C
ORG
V
CC
V
SS
Chip Select Input
ERAL
WRAL
Serial Data Input
Serial Data Output
Serial Clock
Organisation Select
Supply Voltage
Ground
The memory array organization may be divided
into either bytes (x8) or words (x16) which may be
selected by a signal applied on Organization Se-
lect (ORG). The bit, byte and word sizes of the
memories are as shown in Table 2.
A Read Data from Memory (READ) instruction
loads the address of the first byte or word to be
read in an internal address register. The data at
this address is then clocked out serially. The ad-
dress register is automatically incremented after
the data is output and, if Chip Select Input (S) is
held High, the M93Cx6 can output a sequential
stream of data bytes or words. In this way, the
memory can be read as a data stream from eight
to 16384 bits long (in the case of the M93C86), or
continuously (the address counter automatically
rolls over to 00h when the highest address is
reached).
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an Erase cycle prior to the Write
instruction. The Write instruction writes 8 or 16 bits
at a time into one of the byte or word locations of
the M93Cx6. After the start of the programming cy-
2/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
en High.
An internal Power-on Data Protection mechanism
in the M93Cx6 inhibits the device when the supply
is too low.
Figure 3. DIP, SO and TSSOP Connections
MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to V
CC
)
the x16 organization is selected; when Organiza-
tion Select (ORG) is connected to Ground (V
SS
)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to V
SS
or V
CC
for minimum
power consumption. Any voltage between V
SS
and V
CC
applied to Organization Select (ORG)
may increase the stand-by current.
The DU (Don’t Use) pin does not contribute to the
normal operation of the device. It is reserved for
use by STMicroelectronics during test sequences.
The pin may be left unconnected or may be con-
nected to V
CC
or V
SS
. Direct connection of DU to
V
SS
is recommended for the lowest stand-by pow-
er consumption.
M93Cx6
S
C
D
Q
1
2
3
4
8
7
6
5
AI01929B
VCC
DU
ORG
VSS
Note: 1. See page 21 (onwards) for package dimensions, and how
to identify pin-1.
2. DU = Don’t Use.
Figure 4. 90° Turned-SO Connections
M93Cx6
DU
VCC
S
C
1
2
3
4
8
7
6
5
AI00900B
ORG
VSS
Q
D
Note: 1. See page 24 for package dimensions, and how to identify
pin-1.
2. DU = Don’t Use.
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode.
– At Power-up and Power-down, the device must
not
be selected (that is, Chip Select Input (S)
must be driven Low) until the supply voltage
reaches the operating value V
CC
specified in
Table 8 to Table 10.
– When V
CC
reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming in-
structions.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6-
W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
3/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
INSTRUCTIONS
The instruction set of the M93Cx6 devices con-
tains seven instructions, as summarized in Table 4
to Table 6. Each instruction consists of the follow-
ing parts, as shown in Figure 5:
s
Each instruction is preceded by a rising edge on
Chip Select Input (S) with Serial Clock (C) being
held Low.
s
s
A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
Two op-code bits, read on Serial Data Input (D)
during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
The address bits of the byte or word that is to be
accessed. For the M93C46, the address is
made up of 6 bits for the x16 organization or 7
bits for the x8 organization (see Table 4). For
the M93C56 and M93C66, the address is made
up of 8 bits for the x16 organization or 9 bits for
the x8 organization (see Table 5). For the
M93C76 and M93C86, the address is made up
of 10 bits for the x16 organization or 11 bits for
the x8 organization (see Table 6).
s
The M93Cx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in Table 19 to Table 22.
Table 4. Instruction Set for the M93C46 and M93C06
x8 Origination (ORG = 0)
Instruc
tion
Description
Start
bit
Op-
Code
Address
1,2
Data
x16 Origination (ORG = 1)
Data
Required
Clock
Cycles
Required
Clock
Address
1,3
Cycles
A5-A0
18
10
10
10
10
D7-D0
18
A5-A0
11 XXXX
00 XXXX
A5-A0
10 XXXX
01 XXXX
D15-D0
READ
WRITE
EWEN
EWDS
ERASE
ERAL
WRAL
Read Data from
Memory
Write Data to
Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
Write All Memory
with same Data
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A6-A0
A6-A0
11X XXXX
00X XXXX
A6-A0
10X XXXX
01X XXXX
Q7-Q0
D7-D0
Q15-Q0
D15-D0
25
9
9
9
9
25
Note: 1. X = Don’t Care bit.
2. Address bits A6 and A5 are not decoded by the M93C06.
3. Address bits A5 and A4 are not decoded by the M93C06.
4/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 5. Instruction Set for the M93C56 and M93C66
x8 Origination (ORG = 0)
Instruc
tion
Description
Start
bit
Op-
Code
Address
1,2
x16 Origination (ORG = 1)
Data
Required
Clock
Cycles
Data
Required
Clock
Address
1,3
Cycles
A7-A0
20
12
12
12
12
A7-A0
11XX
XXXX
00XX
XXXX
A7-A0
10XX
XXXX
01XX
XXXX
READ
WRITE
EWEN
EWDS
ERASE
ERAL
WRAL
Read Data from
Memory
Write Data to
Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
Write All Memory
with same Data
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A8-A0
A8-A0
1 1XXX
XXXX
0 0XXX
XXXX
A8-A0
1 0XXX
XXXX
0 1XXX
XXXX
Q7-Q0
D7-D0
Q15-Q0
D15-D0
27
11
11
11
11
D15-D0
27
D7-D0
20
Note: 1. X = Don’t Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction Set for the M93C76 and M93C86
x8 Origination (ORG = 0)
Instruc
tion
Description
Start
bit
Op-
Code
Address
1,2
x16 Origination (ORG = 1)
Data
Required
Clock
Cycles
Data
Required
Clock
Address
1,3
Cycles
A9-A0
22
14
14
14
14
A9-A0
11 XXXX
XXXX
00 XXXX
XXXX
A9-A0
10 XXXX
XXXX
01 XXXX
XXXX
READ
WRITE
EWEN
EWDS
ERASE
ERAL
WRAL
Read Data from
Memory
Write Data to
Memory
Erase/Write Enable
Erase/Write Disable
Erase Byte or Word
Erase All Memory
Write All Memory
with same Data
1
1
1
1
1
1
1
10
01
00
00
11
00
00
A10-A0
A10-A0
11X XXXX
XXXX
00X XXXX
XXXX
A10-A0
10X XXXX
XXXX
01X XXXX
XXXX
Q7-Q0
D7-D0
Q15-Q0
D15-D0
29
13
13
13
13
D15-D0
29
D7-D0
22
Note: 1. X = Don’t Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
5/27
TI Technology Forum
京公网安备 11010802033920号
EEWORLD
