5-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller
ADP3166
*
FEATURES
Selectable 2-, 3- or 4-Phase Operation at up to
1 MHz per Phase
Differential Sensing Error
±1%
over Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly
VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable
Latch-Off Delay
Overvoltage Protection Crowbar Logic Output
APPLICATIONS
Desktop PC Power Supplies
Next-Generation AMD Processors
VRM Modules
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
VCC
28
RAMPADJ RT
14
13
ADP3166
EN 11
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
+
GND 19
CROWBAR 6
CSREF
2.1V
DAC + 300mV
CSREF
+
–
DAC – 300mV
23 SW1
PWRGD 10
DELAY
22 SW2
21 SW3
ILIMIT 15
EN
CURRENT
LIMIT
CIRCUIT
–
+
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
SOFT
START
COMP 9
–
+
+
–
8 FB
+
–
+
–
CURRENT
BALANCING
CIRCUIT
+
–
CMP
–
CMP
SET
RESET
EN
27 PWM1
+
–
CMP
RESET
2-, 3- , 4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
+
–
CMP
RESET
24 PWM4
CROWBAR
CURRENT
LIMIT
The ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch-
ing stages.
The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt-
age changes requested by the CPU.
ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
DELAY 12
PRECISION
REFERENCE
7
FBRTN
1
VID4
2
VID3
VID
DAC
3
VID2
4
VID1
5
VID0
*Patent
pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADP3166–SPECIFICATIONS
1
(V
Parameter
ERROR AMPLIFIER
Accuracy
0.8 V Output
1.175 V Output
1.55 V Output
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time
2
No CPU Detection Turn-Off
Delay Time
2
OSCILLATOR
Frequency Range
2
Frequency Variation
∆V
FB
I
FB
I
FBRTN
I
O(ERR)
GBW
(ERR)
Symbol
V
FB
CC
= 12 V, FBRTN = GND, T
A
= 0 C to 85 C, unless otherwise noted.)
Min
Typ
Max
Unit
Conditions
Referenced to FBRTN, CSSUM = CSCOMP, 0.792 0.800 0.808
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP, 1.163 1.175 1.187
See Test Circuit 1
Referenced to FBRTN, CSSUM = CSCOMP, 1.535 1.55 1.566
See Test Circuit 1
VCC = 10 V to 14 V
0.05
–13
–15.5 –17
100
200
FB forced to V
OUT
– 3%
500
COMP = FB
20
C
COMP
= 10 pF
50
0.8
2
VID(X) = 0 V
100
2.0
400
400
20
120
2.4
26
2.65
V
V
V
%
µA
µA
µA
MHz
V/µs
V
V
µA
kΩ
V
ns
ns
V
IL(VID)
V
IH(VID)
I
VID
R
VID
VID code change to FB change
VID code change to 11111 to
PWM going low
f
OSC
f
PHASE
V
RT
V
RAMPADJ
I
RAMPADJ
V
OS(CSA)
I
BIAS(CSA)
GBW
CSA
∆V
FB
I
CSCOMP
V
SW(X)CM
R
SW(X)
I
SW(X)
∆I
SW(X)
Output Voltage
Timing Resistor Value
RAMPADJ Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
In Shutdown
Output Current, Normal Mode
Maximum Output Current
Current Limit Threshold Voltage
Current Limit Setting Ratio
Latch-Off Delay Threshold
Latch-Off Delay Time
T
A
= 25°C, R
T
= 250 kΩ, 4-phase
T
A
= 25°C, R
T
= 115 kΩ, 4-phase
2
T
A
= 25°C, R
T
= 75 kΩ, 4-phase
2
R
T
= 100 kΩ to GND
RAMPADJ – FB
0.25
160
1.9
–50
0
–3
200
400
600
2.0
4
240
2.1
500
+50
50
+3
100
MHz
kHz
kHz
kHz
V
kΩ
mV
µA
mV
nA
MHz
V/µs
V
mV
V
µA
mV
kΩ
µA
%
CSSUM – CSREF, see Test Circuit 2
C
CSCOMP
= 10 pF
CSSUM and CSREF
See Test Circuit 3
I
CSCOMP
=
±
100
µA
20
20
50
0
–76
0.05
–80
500
–600
24
5
–5
3
–84
3.3
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
+200
36
9
+5
V
ILIMIT(NM)
V
ILIMIT(SD)
I
ILIMIT(NM)
V
CL
V
SET(DLY)
t
SET(DLY)
EN > 2 V
EN < 0.8 V, I
ILIMIT
= –100
µA
EN > 2 V, R
ILIMIT
= 250 kΩ
EN > 2 V
V
CSREF
– V
CSCOMP
, R
ILIMIT
= 250 kΩ
V
CL
/I
ILIMIT
In current limit
R
DELAY
= 250 kΩ, C
DELAY
= 4.7 nF
2.9
3
12
3.1
400
60
105
1.7
125
10.4
1.8
600
145
1.9
V
mV
µA
µA
mV
mV/µA
V
µs
–2–
REV. 0
ADP3166
Parameter
SOFT START
Output Current, Soft Start Mode
Soft Start Delay Time
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Off-State Leakage Current
Delay Time
VID Code Changing
VID Code Static
CROWBAR COMPARATOR
Crowbar Trip Point
Crowbar Reset Point
Crowbar Response Time
Overvoltage to PWM Low
Overvoltage to CRWBR High
Output Voltage Low
Output Voltage High
PWM OUTPUTS
Output Voltage Low
Output Voltage High
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
Symbol
I
DELAY(SS)
t
DELAY(SS)
Conditions
During start-up, DELAY < 2.8 V
R
DELAY
= 250 kΩ, C
DELAY
= 4.7 nF
VID Code = 01111
Min
15
Typ
20
350
Max
25
Unit
µA
µs
V
IL(EN)
V
IH(EN)
0.8
2
–1
Relative to nominal DAC output
Relative to nominal DAC output
I
PWRGD(SINK)
= 4 mA
V
CSREF
= V
DAC
–200
200
–300
300
150
+1
–400
400
400
50
V
V
µA
mV
mV
mV
µA
µs
ns
V
PWRGD(UV)
V
PWRGD(OV)
V
OL(PWRGD)
100
250
400
2.1
400
400
400
100
5.0
160
5.0
7
6.9
0.9
2.2
500
V
CROWBAR
t
CROWBAR
V
OL(CROWBAR)
I
CROWBAR(SINK)
= 100
µA
V
OH(CROWBAR)
I
CROWBAR(SOURCE)
= 100
µA
V
OL(PWM)
V
OH(PWM)
I
CC
V
UVLO
I
PWM(SINK)
= 400
µA
I
PWM(SOURCE)
= 400
µA
2.0
300
V
mV
ns
ns
mV
V
mV
V
mA
V
V
500
4.0
500
4.0
VCC rising
6.5
0.7
10
7.3
1.1
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
Guaranteed by design, not tested in production.
Specifications subject to change without notice.
REV. 0
–3–
ADP3166
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP,
CROWBAR, PWM1 to PWM4 . . . . . . . . . –0.3 V to +5.5 V
SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +25 V
All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
ORDERING GUIDE
Model
ADP3166JRU-REEL7
ADP3166JRU-REEL
Temperature
Range
0°C to 85°C
0°C to 85°C
Package
Options
RU-28 (TSSOP-28)
RU-28 (TSSOP-28)
Quantity
per Reel
1000
2500
5.3
T
A
= 25 C
4-PHASE OPERATION
5.2
4
MASTER CLOCK FREQUENCY – MHz
0
0.5
1.0
1.5
2.0
2.5
3.0
MASTER CLOCK FREQUENCY – MHz
3.5
4.0
SUPPLY CURRENT – mA
3
5.1
5.0
2
4.9
4.8
1
4.7
4.6
0
0
50
100
150
200
RT VALUE – kΩ
250
300
TPC 1. Supply Current vs. Master Clock Frequency
TPC 2. Master Clock Frequency vs. R
T
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADP3166
ADP3166
1
VID4
2
VID3
3
VID2
VCC
28
PWM1
27
PWM2
26
PWM3
25
PWM4
24
SW1
23
SW2
22
SW3
21
+
1 F
12V
100nF
12V
28
ADP3166
VCC
5-BIT CODE
4
VID1
5
VID0
6
CROWBAR
7
FBRTN
8
FB
9
COMP
FB
8
10k
COMP
9
200k
18
CSCOMP
200k
1k
10
PWRGD
17
GND
19
CSCOMP
18
20k
100nF
CSSUM
17
CSREF
16
ILIMIT
15
250k
80mV
CSREF
16
1.25V
11
EN
12
DELAY
1V
+
–
19
GND
4.7nF
250k
V
FB
= FB – V
VID
13
RT
14
RAMPADJ
Test Circuit 1. Closed-Loop Output Voltage Accuracy
Test Circuit 3. Positioning Voltage Test Circuit
ADP3166
VCC
12V
28
CSCOMP
18
100nF
39k
CSSUM
17
1k
16
CSREF
+
–
19
1V
GND
V
OS
= CSCOMP – 1V
40
Test Circuit 2. Positioning Amplifier V
OS
Test Circuit
REV. 0
–5–
+
+
–
–
SW4
20
CSSUM
+
–
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