TLP2200
TOSHIBA Photocoupler
GaAℓAs Ired & Photo-IC
TLP2200
Isolated Buss Driver
High Speed Line Receiver
Microprocessor System Interfaces
MOS FET Gate Driver
Direct Replacement For HCPL−2200
The TOSHIBA TLP2200 consists of a GaAℓAs light
emitting diode and integrated high gain, high speed
photodetector.
This unit is 8−lead DIP package.
The detector has a three state output stage that
eliminates the need for pull−up resistor, and built−in
schmitt trigger. The detector IC has an internal shield
that provides a guaranteed common mode transient
immunity of 1000V /
μs.
Input current: I
F
= 1.6mA
Power supply voltage: V
CC
= 4.5~20V
Switching speed: 2.5MBd guaranteed
Common mode transient immunity: ±1000V /
μs
(min.)
Guaranteed performance over temp: 0~85°C
Isolation voltage: 2500Vrms(min.)
UL recognized: UL1577, file No. E67349
1
V
CC
8
7
6
GND
SHIELD
5
Unit in mm
TOSHIBA
11−10C4
Weight: 0.54 g (typ.)
Pin Configuration (top view)
1: N.C.
2: Anode
3: Cathode
4: N.C.
5: GND
6: V
E
(enable)
7: V
O
(output)
8: V
CC
Truth Table
(positive logic)
Input
H
L
H
L
Enable
H
H
L
L
Output
Z
Z
H
L
2
3
4
Schematic
I
F
2
V
F
3
I
E
I
CC
I
O
8
7
6
SHIELD
5
V
CC
V
O
V
E
GND
1
2007-10-01
TLP2200
Recommended Operating Conditions
Characteristic
Input current, on
Input current, off
Supply voltage
Enable voltage high
Enable voltage low
Fan out (TTL load)
Operating temperature
Symbol
I
F(ON)
I
F(OFF)
V
CC
V
EH
V
EL
N
T
opr
Min.
1.6
0
4.5
2.0
0
―
0
Typ.
―
―
―
―
―
―
―
Max.
5
0.1
20
20
0.8
4
85
Unit
mA
mA
V
V
V
―
°C
Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the
device. Additionally, each item is an independent guideline respectively. In developing designs using this
product, please confirm specified characteristics shown in this document.
Absolute Maximum Ratings
(no derating required up to 70°C)
Characteristic
L E D
Forward current
Peak transient forward current
Reverse voltage
Output current
Supply voltage
Output voltage
Three state enable voltage
Total package power dissipation
(Note 2)
(Note 1)
Symbol
I
F
I
FPT
V
R
I
O
V
CC
V
O
V
E
P
T
T
opr
T
stg
T
sol
BV
S
Rating
10
1
5
25
−0.5~20
−0.5~20
−0.5~20
210
−40~85
−55~125
260
2500
Unit
mA
A
V
mA
V
V
V
mW
°C
°C
°C
Vrms
Operating temperature range
Storage temperature range
Lead solder temperature (10s) (**)
Isolation voltage (AC 1min., R.H.
≤
60%,Ta = 25°C)
(Note 3)
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
(Note 1) Pulse width 1μs 300pps.
(Note 2) Derate 4.5mW / °C above 70°C ambient temperature.
(Note 3) Device considered a two terminal device: Pins 1, 2, 3 and 4 shorted together, and pins 5,6,7 and 8 shorted
together
(**)
1.6mm below seating plane.
D e t e c t o r
2
2007-10-01
TLP2200
Electrical Characteristics
(unless otherwise specified, Ta = 0~85°C,V
CC
= 4.5~20V
,
I
F(ON)
= 1.6~5mA, I
F(OFF)
= 0~0.1mA, V
EL
= 0~0.8V,V
EH
= 2.0~20V)
Characteristic
Output leakage current
(V
O
> V
CC
)
Logic low output voltage
Logic high output voltage
Logic low enable current
Symbol
I
OHH
V
OL
V
OH
I
EL
I
EH
V
EL
V
EH
I
CCL
I
CCH
I
OZL
High impedance state
output current
I
OZH
I
OSL
I
OSH
I
HYS
V
F
ΔV
F
/
ΔTa
BV
R
C
IN
R
I−O
C
I−O
I
F
= 0mA
V
E
= don't care
I
F
= 5mA
V
E
= don't care
I
F
= 5mA
V
E
= 2V
I
F
= 0mA
V
E
= 2V
I
F
= 0mA
I
F
= 5mA
V
O
= GND
V
CC
= 5V
I
F
= 5mA, Ta = 25°C
I
F
= 5mA
I
R
= 10μA, Ta = 25°C
V
F
= 0V, f = 1MHz, Ta = 25°C
V
I−O
= 500V R.H.
≤
60%
V
I−O
= 0V, f = 1MHz
Test Condition
I
F
= 5mA,
V
CC
= 4.5V
V
O
= 5.5V
V
O
= 20V
Min.
―
―
―
2.4
―
―
―
―
―
―
V
CC
= 5.5V
V
CC
= 20V
V
CC
= 5.5V
V
CC
= 20V
V
O
= 0.4V
V
O
= 2.4V
V
O
= 5.5V
V
O
= 20V
V
O
= V
CC
= 5.5V
V
O
= V
CC
= 20V
V
CC
= 5.5V
V
CC
= 20V
―
2.0
―
―
―
―
―
―
―
―
25
40
−10
−25
―
―
―
5
―
10
Typ.*
―
2
0.32
3.4
−0.13
―
―
0.01
―
―
5
5.6
2.5
2.8
1
―
―
0.01
55
80
−25
−60
0.05
1.55
−2.0
―
45
10
14
Max.
100
500
0.5
―
−0.32
20
100
250
0.8
―
6.0
7.5
4.5
6.0
−20
20
100
500
―
―
―
―
―
1.7
―
―
―
―
―
Unit
μA
V
V
mA
μA
I
OL
= 6.4mA (4 TTL load)
I
OH
=
−2.6mA
V
E
= 0.4V
V
E
= 2.7V
V
E
= 5.5V
V
E
= 20V
Logic high enable current
Logic low enable voltage
Logic high enable voltage
Logic low supply current
Logic high supply current
V
V
mA
mA
μA
Logic low short circuit
output current
Logic high short circuit
output current
Input current hysteresis
Input forward voltage
(Note 4)
(Note 4)
mA
mA
mA
V
mV / °C
V
pF
Ω
pF
Temperature coefficient of
forward voltage
Input reverse breakdown
voltage
Input capacitance
Resistance (input−output)
Capacitance (input−output)
(Note 3) 5×10
(Note 3)
―
0.6
(**) All typ. values are at Ta = 25°C, V
CC
= 5V, I
F(ON)
= 3mA unless otherwise specified.
3
2007-10-01
TLP2200
Switching Characteristics
(unless otherwise specified, Ta = 0~85°C,V
CC
= 4.5~20V,I
F(ON)
= 1.6~5mA,I
F(OFF)
= 0~0.1mA)
Characteristic
Propagation delay time to
logic high output level
(Note 5)
Propagation delay time to
logic low output level
(Note 5)
Output rise time (10−90%)
Output fall time (90−10%)
Output enable time to
logic high
Output enable time to
logic low
Output disable time from
logic high
Output disable time from
logic low
Common mode transient
immunity at logic high
output
(Note 6)
Common mode transient
immunity at logic low
output
(Note 6)
t
r
t
f
t
pZH
t
pZL
2
t
pHZ
t
pLZ
CM
H
3
CM
L
I
F
= 0mA, V
CM
= 50V,
Ta = 25°C
1000
―
―
V /
μs
―
―
I
F
= 1.6mA, V
CM
= 50V,
Ta = 25°C
―
―
−1000
―
―
―
―
―
―
ns
ns
V /
μs
t
pHL
1
Symbol
Test
Cir−
cuit
Test Condition
Without peaking capacitor
C
1
With peaking capacitor C
1
Without peaking capacitor
C
1
With peaking capacitor C
1
―
―
―
Min.
―
―
―
―
―
―
―
―
Typ.
235
―
250
―
35
20
―
―
Max.
―
400
―
400
―
―
―
―
ns
ns
ns
ns
ns
Unit
t
pLH
ns
(*) All typ. values are at Ta = 25°C, V
CC
= 5V, I
F(ON)
= 3mA unless otherwise specified.
(Note 4) Duration of output short circuit time should not exceed 10ms.
(Note 5) The t
pLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the
1.3V point on the leading edge of the output pulse.
The t
pHL
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the trailing edge of the output pulse.
(Note 6) CM
L
is the maximum rate of rise of the common mode voltage that can be sustained with the output
voltage in the logic low state (V
O
≤
0.8V).
CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output
voltage in the logic high state (V
O
≤
2.0V).
4
2007-10-01
TLP2200
Test Circuit 1
t
pHL
,
t
pLH
,
t
r
and t
f
Pulse
Generator
t
r
= t
f
= 5ns
V
O
= 5V
I
F
(ON)
50%
Input I
F
t
p
LH
90%
Output V
O
10%
t
r
t
p
HL
1.3V
t
f
V
OL
0mA
V
OH
Input
Monitoring
Node
R
1
1
2
3
4
C1=120pF
GND
V
CC
Output V
O
Monitoring
Node
V
CC
619Ω
D1
6
5
C
L
5kΩ
V
CC
V
O
1
I
F
2
3
Input V
E
Monitoring
Node
4
GND
V
CC
8
7
5kΩ
6
5
C
L
D1
619Ω
S2
8
7
D2
D3
D4
5V
D1~D4
: 1S1588
R
1
I
F
(ON)
2.15kΩ
1.6mA
1.1kΩ
3mA
681Ω
5mA
C
1
is peaking capacitor. The probe and jig
capacitances are include in C
1
.
C
L
is approximately 15pF which includes probe
and stray wiring capacitance.
Test Circuit 2 t
pHZ
,
t
pZH
,
t
pLZ
and t
pZL
Pulse
Generator
Z
O
= 50Ω
t
r
= t
f
= 5ns
3.0V
Input V
E
Output V
O
I
F
=I
F
(OFF)
S1 Closed
S2 Open
Output V
O
I
F
=I
F
(ON)
S1 Open
S2 Closed
t
P
ZL
1.3V
t
P
ZH
1.3V
0V
V
OH
~
~1.5V
S1 and S2
Closed
C
L
is approximately 15pF which includes probe
and stray wiring capacitance.
t
P
LZ
0.5V
1.3V
0V
S1 and S2
Closed
V
OL
5V
S1
D1~D4
: 1S1588
D2
D3
D4
t
P
HZ 0.5V
5
2007-10-01
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