A3977
Microstepping DMOS Driver with Translator
Features and Benefits
▪
±2.5 A, 35 V output rating
▪
Low r
DS(on)
outputs, 0.45
Ω
source, 0.36
Ω
sink typical
▪
Automatic current decay mode detection/selection
▪
3.0 to 5.5 V logic supply voltage range
▪
Mixed, fast, and slow current decay modes
▪
Home output
▪
Synchronous rectification for low power dissipation
▪
Internal UVLO and thermal shutdown circuitry
▪
Crossover-current protection
Description
The A3977 is a complete microstepping motor driver, with built-
in translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive
capability of 35 V and ±2.5 A. The A3977 includes a fixed
off-time current regulator that has the ability to operate in
slow-, fast-, or mixed-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3977. Simply inputting one pulse on the STEP input drives the
motor one step (two logic inputs determine if it is a full-, half-,
quarter-, or eighth-step). There are no phase-sequence tables,
high-frequency control lines, or complex interfaces to program.
The A3977 interface is an ideal fit for applications where a
complex microprocessor is unavailable or over-burdened.
Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage lockout (UVLO) and crossover-current
protection. Special power-up sequencing is not required.
The A3977 is supplied in a choice of two power packages, a
44-pin plastic PLCC with 3 internally-fused pins on each of
four sides (suffix ED), and a thin (<1.2 mm), 28-pin TSSOP
with an exposed thermal pad (suffix LP). Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.
Packages:
Package ED, 44-pin PLCC
with internally fused pins
Package LP, 28-pin TSSOP
with exposed thermal pad
Not to scale
Pin-out Diagram
LOAD
SUPPLY
1
SENSE
1
ENABLE
OUT
1A
HOME
GND
GND
GND
DIR
SLEEP
OUT
1B
6
5
4
3
2
1
44
43
V
BB1
42
41
40
NC
NC
PFD
7
CHARGE PUMP
39 NC
38 CP
2
37 CP
1
36 V
CP
35 GND
34 GND
33 GND
REG
32
V
REG
8
9
PWM
TIMER
RC
1
10
GND 11
GND 12
GND 13
REF 14
RC
2
15
LOGIC
SUPPLY 16
NC 17
V
BB2
18
OUT
2A
TRANSLATOR
& CONTROL LOGIC
÷8
31 STEP
V
DD
30 NC
29 NC
19
MS
2
20
MS
1
21
SENSE
2
22
GND
23
GND
24
GND
25
SUPPLY
LOAD
2
26
SR
27
RESET
28
OUT
2B
Dwg. PP-075-1
26184.22K
A3977
Microstepping DMOS Driver with Translator
Selection Guide
Part Number
Packing
Package
Ambient Temperature, T
A
(°C)
A3977KEDTR-T*
450 per reel
44-pin PLCC
–40 to 125
A3977SEDTR-T*
450 per reel
44-pin PLCC
–20 to 85
A3977SLPTR-T
4000 per reel
28-pin TSSOP
–20 to 85
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the
variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer
applications. The variant should not be purchased for new design applications because of obsolescence in the
near future. Samples are no longer available. Status date change April 23, 2013. Deadline for receipt of LAST
TIME BUY orders is September 30, 2013.
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic Supply Voltage
Logic Input Voltage Range
Reference Voltage
Sense Voltage (DC)
Symbol
V
BB
V
DD
V
IN
V
REF
V
SENSE
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Output Current
I
OUT
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
T
A
T
J
(max)
T
stg
Range K
Range S
–40 to 125
–20 to 85
150
–55 to 150
ºC
ºC
ºC
ºC
±2.5
A
Pulsed, t
w
> 30 ns
Pulsed, t
w
< 30 ns
Notes
Rating
35
7.0
–0.3 to V
DD
+ 0.3
–1.0 to V
DD
+ 1
V
DD
0.5
Units
V
V
V
V
V
V
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
Package ED, on 4-layer PCB based on JEDEC standard
Package LP, on 4-layer PCB based on JEDEC standard
Value Units
22
28
ºC/W
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3977
Microstepping DMOS Driver with Translator
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
VDD
REF.
SUPPLY
REF
UVLO
AND
FAULT
2V
REGULATOR
BANDGAP
VREG
CP2
CP1
VCP
LOAD
SUPPLY
CHARGE
PUMP
VBB1
DMOS H BRIDGE
DAC
+ -
SENSE1
VCP
RC1
PWM LATCH
BLANKING
4
STEP
MIXED DECAY
PWM TIMER
OUT 1A
OUT1B
MS 1
MS 2
HOME
SLEEP
V
PFD
SR
CONTROL LOGIC
GATE DRIVE
RESET
TRANSLATOR
DIR
SENSE1
DMOS H BRIDGE
VBB2
OUT 2A
OUT2B
ENABLE
PWM TIMER
4
PWM LATCH
BLANKING
MIXED DECAY
PFD
RC 2
+
DAC
-
SENSE2
Dwg. FP-050-2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3977
LP Pin-out
(TSSOP)
Microstepping DMOS Driver with Translator
Table 1. Microstep Resolution Truth Table
MS
1
L
H
L
H
MS
2
L
L
H
H
Resolution
Full step (2 phase)
Half step
Quarter step
Eighth step
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3977
Microstepping DMOS Driver with Translator
ELECTRICAL CHARACTERISTICS at T
A
= +25°C, V
BB
= 35 V, V
DD
= 3.0 V to 5.5V (unless otherwise noted)
Characteristic
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
V
BB
I
DSS
r
DS(on)
V
F
Operating
During sleep mode
V
OUT
= V
BB
V
OUT
= 0 V
Source driver, I
OUT
= -2.5 A
Sink driver, I
OUT
= 2.5 A
Source diode, I
F
= -2.5 A
Sink diode, I
F
= 2.5 A
f
PWM
< 50 kHz
Motor Supply Current
I
BB
Operating, outputs disabled
Sleep mode
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
Maximum STEP Frequency
HOME Output Voltage
Blank Time
Fixed Off Time
Mixed Decay Trip Point
Ref. Input Voltage Range
Reference Input Current
Gain (Gm) Error (note 3)
Crossover Dead Time
V
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
f
STEP
V
OH
V
OL
t
BLANK
t
off
PFDH
PFDL
VREF
IREF
VREF = 2 V, Phase Current = 38.27%
EG
tDT
VREF = 2 V, Phase Current = 70.71%
VREF = 2 V, Phase Current = 100.00%
SR enabled
Operating
I
OH
= -200
μA
I
OL
= 200
μA
R
t
= 56 kΩ, C
t
= 680 pF
R
t
= 56 kΩ, C
t
= 680 pF
V
IN
= 0.7V
DD
V
IN
= 0.3V
DD
Operating
3.0
0.7V
DD
–
-20
-20
500*
0.7V
DD
–
700
30
–
–
0
–
–
–
–
100
5.0
–
–
<1.0
<1.0
–
–
–
950
38
0.6VDD
0.21VDD
–
0
–
–
–
475
5.5
–
0.3V
DD
20
20
–
–
0.3V
DD
1200
46
–
–
VDD
±3.0
±10
±5.0
±5.0
800
V
V
V
μA
μA
kHz
V
V
ns
μs
V
V
V
μA
%
%
%
ns
8.0
0
–
–
–
–
–
–
–
–
–
–
–
<1.0
<1.0
0.45
0.36
–
–
–
–
–
35
35
20
-20
0.57
0.43
1.4
1.4
8.0
6.0
20
V
V
μA
μA
Ω
Ω
V
V
mA
mA
μA
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5