CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
■
■
■
True dual-ported memory cells that allow simultaneous access
of the same memory location
Six flow through/pipelined devices:
❐
16K x 16/18 organization (CY7C09269V/369V)
❐
32K x 16/18 organization (CY7C09279V/379V)
❐
64K x 16/18 organization (CY7C09289V/389V)
Three modes:
❐
Flow through
❐
Pipelined
❐
Burst
Pipelined output mode on both ports allows fast 100 MHz
operation
0.35 micron CMOS for optimum speed and power
High speed clock to data access: 6.5
[1, 2]
, 7.5
[2]
, 9, 12 ns (max)
3.3V low operating power:
❐
Active = 115 mA (typical)
❐
Standby = 10
μA
(typical)
Fully synchronous interface for easier operation
Burst counters increment addresses internally:
❐
Shorten cycle times
❐
Minimize bus noise
❐
Supported in flow through and pipelined modes
Dual chip enables easy depth expansion
Upper and lower byte controls for bus matching
Automatic power down
Commercial and industrial temperature ranges
Pb-Free 100-pin TQFP package available
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
I/O
8/9L
–I/O
15/17L
[4]
8/9
14/15/16
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
8/9
[3]
8/9
I/O
8/9R
–I/O
15/17R
I/O
Control
I/O
Control
8/9
14/15/16
[3]
[4]
I/O
0L
–I/O
7/8L
A
0L
–A
13/14/15L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[5]
I/O
0R
–I/O
7/8R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
A
0R
–A
13/14/15R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[5]
True Dual-Ported
RAM Array
Notes
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
4. I/O
0
–I/O
7
for x16 devices. I/O
0
–I/O
8
for x18 devices.
5. A
0
–A
13
for 16K; A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 25, 2009
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Definitions
Left Port
A
0L
–A
15L
ADS
L
Right Port
A
0R
–A
15R
ADS
R
Description
Address Inputs
(A
0
–A
14
for 32K, A
0
–A
13
for 16K devices).
Address Strobe Input.
Used as an address qualifier. This signal must be asserted LOW to access
the part using an externally supplied address. Asserting this signal LOW also loads the burst counter
with the address present on the address pins.
Chip Enable Input.
To select either the left or right port, both CE
0
AND CE
1
must be asserted to their
active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal.
This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input.
Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW.
Counter Reset Input.
Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output
(I/O
0
–I/O
15
for x16 devices).
Lower Byte Select Input.
Asserting this signal LOW enables read and write operations to the lower
byte. (I/O
0
–I/O
8
for x18, I/O
0
–I/O
7
for x16) of the memory array. For read operations both the LB and
OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input.
Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input.
This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input.
This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
Flow Through/Pipelined Select Input.
For flow through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads/writes one word from or into
each successive address location, until CNTEN is deasserted.
The counter can address the entire memory array and loop back
to the start. Counter Reset (CNTRST) is used to reset the burst
counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
CE
0L
, CE
1L
CLK
L
CNTEN
L
CNTRST
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
R
I/O
0L
–I/O
17L
I/O
0R
–I/O
17R
LB
L
LB
R
UB
L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
UB
R
OE
R
R/W
R
FT/PIPE
R
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory
[11]
. Registers on control, address, and data
lines allow for minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid t
CD2
= 6.5 ns
[1, 2]
(pipelined). Flow through mode can also
be used to bypass the pipelined output register to eliminate
access latency. In flow through mode, data is available t
CD1
=
18 ns after the address is clocked into the device. Pipelined
output or flow through mode is selected through the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW to HIGH
transition of the clock signal. The internal write pulse is self timed
to allow the shortest possible cycle times.
Note
11. When writing simultaneously to the same location, the final value cannot be guaranteed.
Document #: 38-06056 Rev. *C
Page 4 of 19
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CY7C09269V/79V/89V
CY7C09369V/79V/89V
Maximum Ratings
[12]
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage to Ground Potential
.................−0.5V
to +4.6V
DC Voltage Applied to Outputs
in High Z State
..............................................−0.5V
to V
CC
+0.5V
DC Input Voltage
..........................................−0.5V
to V
CC
+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Electrical Characteristics
Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Parameter
Description
-6
[1, 2]
2.4
0.4
2.0
0.8
–10
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
10
250
115 175
25
95
10
175 320
–10
2.0
0.8
10
155 275
275 390
25
85
85
120
–10
135
185
20
35
95
105
10
10
85
95
2.4
0.4
2.0
0.8
10
230
300
75
85
155
165
250
250
115
125
75
100
10
250
85
140
20
70
–10
115
-7
[2]
2.4
0.4
2.0
0.8
10
180
-9
Typ Max Min
2.4
0.4
-12
Typ Max
V
V
V
V
μA
mA
mA
mA
mA
mA
mA
μA
μA
mA
mA
Unit
Min Typ Max Min Typ Max Min
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
Output HIGH Voltage
(V
CC
= Min. l
OH
= –4.0 mA)
Output LOW Voltage
(V
CC
= Min. l
OH
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current
(V
CC
= Max, I
OUT
= 0 mA)
Outputs Disabled
Standby Current
(Both Ports TTL Level)
[13]
CE
L
& CE
R
≥
V
IH
, f = f
MAX
Standby Current
(One Port TTL Level)
[13]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
I
SB1
I
SB2
105 165
165 210
10
10
250
250
125
I
SB3
Com’l.
Standby Current
(Both Ports CMOS Level)
[13]
Indust.
CE
L
& CE
R
≥
V
CC
– 0.2V, f = 0
Standby Current
(One Port CMOS Level)
[13]
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Com’l.
Indust.
I
SB4
105 135
95
125 170
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max
10
10
Unit
pF
pF
Notes
12. The voltage on any input or I/O pin can not exceed the power pin during power up.
13. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
and CE
1
must be asserted to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Document #: 38-06056 Rev. *C
Page 5 of 19
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