EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

74F399SJX

Description
IC register quad 2port 16sop
Categorylogic    logic   
File Size74KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

74F399SJX Overview

IC register quad 2port 16sop

74F399SJX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP16,.3
Contacts16
Reach Compliance Codecompli
Other featuresFOUR 2:1 MUX FOLLOWED BY REGISTER
seriesF/FAST
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length10.2 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su100000000 Hz
MaximumI(ol)0.02 A
Humidity sensitivity level1
Number of digits4
Number of functions1
Number of entries2
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)34 mA
propagation delay (tpd)10 ns
Certification statusNot Qualified
Maximum seat height2.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width5.3 mm
minfmax100 MHz
Base Number Matches1

74F399SJX Related Products

74F399SJX 74F399SC_NL
Description IC register quad 2port 16sop D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, TTL, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16
Maker Fairchild Fairchild
Parts packaging code SOIC SOIC
package instruction SOP, SOP16,.3 SOP,
Contacts 16 16
Reach Compliance Code compli unknown
Other features FOUR 2:1 MUX FOLLOWED BY REGISTER FOUR 2:1 MUX FOLLOWED BY REGISTER
series F/FAST F/FAST
JESD-30 code R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e3/e4
length 10.2 mm 9.9 mm
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP
Number of digits 4 4
Number of functions 1 1
Number of terminals 16 16
Maximum operating temperature 70 °C 70 °C
Output polarity COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
propagation delay (tpd) 10 ns 10 ns
Certification status Not Qualified Not Qualified
Maximum seat height 2.1 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES YES
technology TTL TTL
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) MATTE TIN/NICKEL PALLADIUM GOLD
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE
width 5.3 mm 3.9 mm
minfmax 100 MHz 100 MHz
Base Number Matches 1 1
【Qinheng RISC-V core CH582】 5 Bluetooth routine initial evaluation and environment construction
Qinheng provides quite a lot of Bluetooth test routines. This evaluation first builds the test environmentOpen the Peripheral example under BLE, compile and download it to the development board Downlo...
kit7828 Domestic Chip Exchange
Things to note for beginners when designing PCB
Things to note for novices when designing PCBs 1. Single-sided pads: Do not use filler blocks as pads for surface mount components. Single-sided pads should be used. Usually single-sided pads are not ...
fighting Analog electronics
Embedded software learning roadmap!
Embedded learning is a gradual process. If you want to develop in the direction of embedded software, the most common one is embedded Linux. Focusing on this direction, I think it can be divided into ...
jingcheng ARM Technology
RISC-V MCU IDE MRS (MounRiver Studio) development: Solve the problem of RAM usage showing 100% after compilation
In the previous article, we learned how to enable the function of printing FLASH and RAM usage information after programming. However, in actual development, although our program does not use all the ...
Moiiiiilter MCU
FPGA Learning - Introduction to Verilog
1. IntroductionVerilog HDL is a hardware description language specifically used to design digital systems, such as network switches, microprocessors, memories, and even simple flip-flops. Using Verilo...
YvanEE Altera SoC
Let's take a look at the price increase rhythm of 10 major chip manufacturers, starting a new round of price increases
As we enter 2022, price increase letters from major chip manufacturers are still being updated and price increases are still continuing.There have been frequent emergencies recently, including factory...
qwqwqw2088 Talking

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号