correction (FEC) algorithm to overcome errors induced by
noise;
• Sophisticated digital signal processing, noise cancellation,
and distortion correction algorithms. These features correct
for a wide variety of signaling impediments, including
impulsive noise, continuous tone noise, and phase distortion;
• High output, low distortion external amplifier design that
can deliver 1Ap-p into low impedance loads, eliminating
the need for expensive phase couplers in typical residential
applications.
The combination of these special features enable the Power
Line Smart Transceivers to operate reliably in the presence of
consumer electronics, power line intercoms, motor noise, electron-
ic ballasts, dimmers, and other typical sources of interference. The
Power Line Smart Transceivers can communicate over virtually
any AC or DC power mains, as well as unpowered twisted pair, by
way of a low-cost, external coupling circuit.
The PL 3120 Power Line Smart Transceiver is targeted at very
low cost designs that require up to 4K Bytes of application code,
and an ultra-compact 38 TSSOP package. The chip includes 4K
Bytes of EEPROM and 2K Bytes of RAM. The Neuron system
firmware and software application libraries are contained in on-
chip ROM.
The PL 3150 Power Line Smart Transceiver is intended for
applications that need to address up to 58K Bytes of external
memory (16K Bytes is dedicated to the Neuron system firmware)
using a 64 LQFP package. The chip includes 0.5K Bytes of
EEPROM and 2K Bytes of RAM.
The PL 3120 and PL 3150 Power Line Smart Transceivers
operate at either 6.5536MHz or 10.0MHz. The 6.5536MHz clock
frequency enables the Power Line Smart Transceiver to communi-
cate in the CENELEC A-band, which is used for metering and
utility applications. The 10MHz clock frequency supports the
CENELEC C-band, which is used for general purpose signaling
and all non-utility related applications.
Application programs stored in the embedded EEPROM
(PL 3120 Power Line Smart Transceiver) or in the external non-
volatile memory (PL 3150 Power Line Smart Transceiver) may be
updated over the power line network. This valuable feature enables
products to be updated without physically accessing them, i.e.,
from a local PC with a power line interface or from a remote
service center through an
i.LON
®
Internet Server. The embedded
EEPROM may be written up to 10,000 times with no data loss.
Data stored in the EEPROM will be retained for at least ten years.
The PL 3120 and PL3150 Power Line Smart Transceivers use
+8.5 to +18VDC and +5VDC power supplies and support very low
receive mode current consumption. The wide power supply range
and very low receive power requirements allow the use of inex-
pensive power supplies.
Additionally, the Power Line Smart Transceivers incorporate a
power management feature that constantly monitors the status of
the device’s power supply. If during transmission the power supply
voltage falls to a level that is insufficient to ensure reliable signal-
ing, the transceiver stops transmitting until the power supply
voltage rises to an acceptable level. This unique feature allows the
use of a power supply with one-third the current capacity other-
wise required. The net result is a reduction in the size, cost, and
thermal dissipation of the power supply. Power management is
especially useful for high volume, low-cost consumer products
such as electrical switches, motion detectors, outlets, light sensors,
and dimmers.
Flexible I/O, Simple Configuration
The PL 3120 and PL 3150 Power Line Smart Transceivers
provide 12 I/O pins which can be configured to operate in one or
more of 38 predefined standard input/output modes. Combining a
wide range of I/O models with two on-board timer/counters
enables the PL 3120 and PL 3150 Power Line Smart Transceivers
to interface with application circuits using minimal external logic
or software development. The Power Line Smart Transceivers also
feature a full duplex hardware UART supporting baud rates of up
to 115kbps, and an SPI interface that operates up to 625kbps.
Inexpensive Power Supply
Only a small number of inexpensive external components are
required to create a complete Power Line Smart Transceiver-based
device (see the PL 3120 / PL 3150 Power Line Smart Transceiver
Block Diagram). These components include:
• Discrete interface circuitry comprised of roughly fifty
components, primarily resistors and capacitors. This circuitry
provides “front-end” filtering for the on-chip A/D, and implements
the power amplifier that drives the on-chip D/A transmit signal
onto the power line. Echelon offers a comprehensive Power Line
Development Support Kit* (DSK) with which customers can
implement this interface circuitry. Contact your salesperson for
details about purchasing a PL DSK.
• Coupling circuit consisting of approximately ten components,
mainly capacitors and inductors, which acts as a simple high-pass
filter located between the Power Line Smart Transceiver and the
power mains. This circuitry provides surge and line transient
protection in addition to blocking the low frequency, 50Hz/60Hz
AC mains signal. Detailed schematics are provided in the
PL 3120
/ PL 3150 Power Line Smart Transceiver Data Book.
• The new RoHS compliant Revision B Power Line Smart
Transceivers eliminate the need for an external inverter, thereby
reducing the cost of external components. Circuits without an
external inverter can only be used with Revision B parts (15311R-
1000 PL 3120 Power Line Smart Transceiver and 15321R-960
PL 3150 Power Line Smart Transceiver).
*Echelon Corporation has developed and patented certain methods of implementing
circuitry external to the PL 3120 and PL 3150 Power Line Smart Transceiver chips.
These patents are licensed pursuant to the Echelon Power Line Smart Transceiver
Development Support Kit License Agreement.
External Components
2
PL 3120 / PL 3150 Power Line Smart Transceiver Block Diagram
General Specifications
Function
Emissions compliance
Description
Designed to be compliant with FCC, Industry Canada, Japan MPT, and CENELEC EN50065-1
specification for low-voltage signaling
5.4kbps raw bit rate in CENELEC C-band and 3.6kbps in CENELEC A-band
Dual Frequency BPSK with DSP-enhanced receiver
132kHz (primary) and 115kHz (secondary) in CENELEC C-band and
86kHz (primary) and 75kHz (secondary) in CENELEC A-band
Models 15311R-1000 and 15321R-960 are designed to be compliant with European Directive
2002/95/EC on Restriction of Hazardous Substances (RoHS) in electrical and electronic
equipment.
Bit rate
Communication technique
Carrier frequencies
RoHS Compliance
PL 3120 Power Line Smart Transceiver Pinout Diagram
38 Pin TSSOP
NOTE:
1
The schematic, bill of materials, and layout plots for the Discrete Interface Circuitry are provided in the PL DSK Power Line Smart Transceiver Development Support Kit.
3
PL 3150 Power Line Smart Transceiver Pinout Diagram
64 Pin LQFP
PL 3120 and PL 3150 Power Line Smart Transceiver Pin Descriptions
Pin Name
XIN
XOUT
RESET
Input
Output
Digital I/O (Built-in Pull-up)
Type
Oscillator connection or external clock input.
Oscillator connection.
Reset pin (active LOW).
Note: The maximum external capacitance is 1000pF.
Service pin (active LOW).
Pin Functions
Digital I/O
(Built-in Configurable Pull-up)
Tie to V
DD5
.
Digital Input
CLKSEL
IO0-IO3
Digital I/O
Large current-sink capacity (20mA). General purpose I/O.
The output of timer/counter 1 may be routed to IO0.
The output of timer/counter 2 may be routed to IO1.
General purpose I/O. The input of timer/counter 1 may be
IO4-IO7, IO11 Digital I/O
(Built-in Configurable Pull-up) one of IO4-IO7. The input of timer/counter 2 is IO4.
IO8
Digital I/O
General purpose I/O. UART RX. SPI slave clock input.
SPI master clock output.
IO9
Digital I/O
General purpose I/O. SPI slave data output. SPI master
data input.
IO10
Digital I/O
General purpose I/O. SPI slave data input. SPI master
data output.
D0-D7
I/O
Bi-directional data bus
R/W
Output
Read/write control output for external memory
4
SERVICE
PL 3120-E4T10
38 TSSOP Pin No.
29
30
35
34
2, 3, 4, 5
6, 7, 8, 9, 33
10
11
36
PL 3150-L10
64 LQFP Pin No.
34
35
49
48
62, 63, 64, 1
2, 3, 4, 13, 47
14
15
50
N/A
N/A
12
12, 11, 10, 9, 8, 7, 6, 5
37
16
Pin Name
E
A0-A15
V
DD5
Output
Output
Power
Power
Power
Type
Enable clock control output for external memory
Memory address output port
Power input (5V nom). All V
DD5
pins must be
connected together externally.
Power input (5V nom). Supplies on-chip analog
circuitry.
Power input (0V, GND). All GND pins must be
connected together externally.
In-circuit test mode control. Driving ICTMode high and
RESET low will place all outputs in high impedance mode
for in-circuit test. Tie to GND for normal operation.
Packet Detect LED driver.
Band in Use LED driver.
Receiver input.
Integrator input and output.
Receive signal.
Comparator to detect when energy storage power supply
lacks sufficient energy to transmit a packet. Tie to VCORE
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