AP105C103KQB2A datasheet, PDF - EEWORLD Datasheet

AP105C103KQB2A: DescriptionCeramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, 15% TC, 0.01uF, Surface Mount, 1210, CHIP; CategoryPassive components capacitor; File Size438KB，4 Pages; ManufacturerAVX

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AP105C103KQB2A Overview

Ceramic Capacitor, Multilayer, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, 15% TC, 0.01uF, Surface Mount, 1210, CHIP

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1869809630
package instruction	CHIP
Reach Compliance Code	not_compliant
Country Of Origin	UK
ECCN code	EAR99
YTEOL	5.63
capacitance	0.01 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	1.02 mm
JESD-609 code	e0
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	RECTANGULAR PACKAGE
Package form	SMT
method of packing	TR, Embossed, 7 Inch
positive tolerance	10%
Rated (DC) voltage (URdc)	50 V
Guideline	TS 16949
size code	1210
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	Tin/Lead (Sn/Pb)
Terminal shape	WRAPAROUND

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