Radiation Hardened
32K x 8 CMOS
EEPROM
Introduction
The W28C256 is a 32K x 8 radiation hardened
EEPROM designed by Sandia National
Laboratories, Albuquerque, NM, and manufactured
by the Northrop Grumman Advanced Technology
Center, Baltimore, MD, using nonvolatile memory
technology transferred from Sandia. It is built
using a mature dual well CMOS process using N
on N+ epitaxial silicon and a two layer interconnect
system.
•
•
•
•
Features
•
1.25 Micrometer Radiation Hardened CMOS on
Epi
- Total Dose up to 300 Krad (Si)
- Transient Logic Upset >5E7 Rad(Si)/sec
- Memory Data Loss >1E12 Rad(Si)/sec
•
Single Event Upsets
- SEU During READ
LETth = 60 MeV/mg/cm
2
- SEU in Address/Data Latches,
LETth = 35 MeV/mg/cm
2
- Permanent SEU damage (During Write Only),
Atomic Number
>
Kr
No Latchup
Compatible with commercial EEPROMs
JEDEC pin compatible in center 28 pins
Full military operating temperature range,
screened to specific test methods for
commercial, Class B, or modified Hi Rel.
Supports these commercial features:
- Self-Timed Programming
- Combined Erase/Write
- Auto Program Start
- +5V only read operation
- Asynchronous Addressing
- 64 Word Page
- Data Polling
VW
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
VSS
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 FP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PE
VDD
WEB
A13
A8
A9
A11
OEB
A10
CEB
D7
D6
D5
D4
D3
RSTB
PINOUT
(Top View)
Absolute Maximum Ratings
SYMBOL
TSTG
TA
VDDR
VW
VTERM
TL
PARAMETER
Storage Temperature
Operating Temperature
Power Supply During Read
External Write Voltage With Respect To VDD
Terminal Voltage With Respect To Ground
Lead Temperature (Soldering 10 sec)
VALUE
-65 TO +150*
-55 TO +125
6
-10.5
6.5
300
UNITS
°C
°C
V
V
V
°C
* See data retention discussion on page 4.
A
6-14
ROW
ADDRESS
LATCHES
COLUMN
ADDRESS
LATCHES
ROW
ADDRESS
DECODER
A
0-5
COLUMN
ADDRESS
DECODER
E
2
MEMORY
ARRAY
LATCH ENABLE
LOAD
WRITE
64 BYTE
PAGE
BUFFER
CE
WE
EDGE
DETECTION
AND
LATCHES
TIMER
LATCH ENABLE
OE
CONTROL
LATCH
CONTROL
LOGIC
VW
I/O BUFFER/
DATA POLLING
PE RSTB
CLK
I/O
0-7
DC Operating Characteristics
T A = -55 to + 125°C, VDD = 5V ±5%, unless otherwise specified
°
LIMITS
SYMBOL
IDDS
IDDR
IDDW
IW1
IDDSB
IIH
IIL
IOH
IOL
VIL
VIH
VOH
VOL
IOZL
IOZH
PARAMETER
Static I Read
Active I Read
Active I Write
Inactive I Write
Standby I
Input I High
Input I Low
Output I High
Output I Low
Input V Low
Input V High
Output V High
Output V Low
Tristate Leakage
Low
Tristate Leakage
High
-10
10
-3
-0.5
3.8
4.25
0.5
0.95
VDD
+0.5
-25
1.5
1
1
3
MIN
MAX
10
17
2
UNITS
mA
mA
mA
uA
mA
uA
uA
mA
mA
V
V
V
V
uA
uA
VDD = 4.75 VW = -4.75 VIH = 3.8 VIL = 0.95 IOL =
-3mA (Note 2)
VDD = 4.75 VW = -4.75 VIH = 3.8 VIL = 0.95 IOH =
3mA (Note 2)
VOH = 4.25V
VOL = 0.5 V
TEST CONDITIONS
Read Mode, DC
Read Mode, 2 MHz
Write Mode
Standby or Read (Note 1)
Notes:
1.
Tested but not recorded
2.
Verified by functional testing
Mode Selection
MODE
Read
Write
Write
Inhibit
CEB
VIL
VIL
X
X
OEB
VIL
X
VIH
X
VIL
WEB
VIH
X
VIL
VIH
X
PE
VIL
VIL
VIL
VIL
VIL
A(12:0)
ADDR
XXX
ADDR
XXX
XXX
I/O
DOUT
HI Z
DIN
HI
Z/DOUT
HI
Z/DOUT
been initiated, the chip may be deselected. When
the part is deselected, the outputs are tristated.
Output Enable (OEB)
This input controls the output buffers. When
HIGH the outputs are tristated and when LOW the
outputs are driven to the correct CMOS levels.
Data (D0-D7)
Data is written to or read from the part using
these pins.
Write Enable (WEB)
This input controls the writing of data. When low,
write is enabled.
Clock Input (CLK)
The clock input is used to time the programming
functions. The nominal value for a 10 ms write
cycle is 2 MHz. The clock is not required for read
Standby VIH
Pin Description Addresses (A0-A14)
The address inputs select which byte will be
accessed during a read or write operation. A0-A5
are the column or byte addresses and A6-A14 are
the row or page addresses.
Chip Enable (CEB)
This input must be LOW during read and write
operations. After a programming operation has
operations. The clock waveform has no critical
timing with respect to other input or output
signals.
Reset Input (RSTB)
The reset input is active LOW and is used to
prevent programming during power transitions or
during high transient radiation doses. This signal
should be held low during power up and power
down.
silicon nitride film, with the silicon dioxide above
and below it acting as energy barriers to the loss
of charge. The charge is injected by tunnelling
through the tunnelling oxide.
The charge deposited in the SONOS dielectric
does decay slowly with time, but when written
under the specified conditions and stored within
the specified limits, data is indeed permanent for
most purposes. Data loss is accelerated by both
temperature and radiation, and is also affected
by the number of write cycles the device has seen
previously.
Write cycles must, however, be accumulated
in the tens of thousands before any effect
on retention is seen. When written using a 2
MHz external clock, nonvolatile data storage
is guaranteed through 100 K Rad (Si), without
rewriting, at the specified temperature range. In
satellite applications, this normally corresponds
to many years of service.
For operation beyond 100 K Rad (Si), data should
be written after every 100 K Rad of accumulated
total dose. In addition to the memory devices
themselves, a key feature of this device is the
radiation hardened peripheral circuitry. This
circuitry remains virtually unaffected by radiation
effects within the limits specified over the full
range of device operation.
For proper retention and reliability, the memory
devices require careful control of the clear/write
conditions. This applies particularly to the control
of the clear/write voltage. The clear/write time
(pulsewidth) is also important.
Consequently, both a Clock pin and a Vwrite pin
are provided. With a nominal 2 MHz clock and
Vw = -5V±5%, this device emulates commercial
EEPROMs. Under these conditions, data retention
is guaranteed for a minimum of 10 years. The
external clock is required for write mode only, read
mode is asynchronous and no clock is required.
Write Voltage (VW)
This -5V±5% supply pin is used to provide the
internal programming voltage. This pin may be
tied to OV during read operations. During power
up VDD must come up first, then Vw; and during
power down Vw must go off first, then VDD.
Program Enable Input (PE)
This pin is used for testing and validation
purposes to gain more control over internal chip
operation. Normal operation requires this pin to
be tied LOW.
Data Polling
The programming time for the W28C256
is controlled by an internal counter and the
externally supplied clock input. The nominal
timing is for a 10 ms programming time with a 2
MHz clock input. The Data Polling mode can be
used to verify the completion of programming. If
a read is performed on any address while the part
is still being programmed, the ones complement
of the last byte written will be presented at the
outputs. After programming has completed, a
read of the last address written will result in the
correct data being presented at the outputs. To
monitor for completion of programming the user
can read the last address written until the correct
data is read.
Data Retention
The W28C256 EEPROM is based on SONOS
nonvolatile memory technology. SONOS is an
acronym for Silicon-Oxide-Nitride-Oxide-Silicon.
The memory device is a silicon gate N-channel
MOS transistor with a specially processed gate
dielectric consisting of a tunnelling oxide, a
silicon nitride layer, and a capping oxide. SONOS
technology is used in preference to conventional
floating gate technology because of its superior
reliability and radiation hardness. The SONOS
memory effect relies on charge storage within the
Temperature
Retention
(Years)
Cycles
Total Dose
K Rad ( Si)
-55 to 80°C
-55 to 80°C
10
10*
10,000 0 to 50
1,000
50 to 100
Rewriting after 100 K Rads results in another 10 years of
retention up to a max total dose specified
AC Operating Characteristics (Write Operations)
T A = -55 to + 125°C, VDD = 5V ±5%, unless otherwise specified
Limits
Symbol
fC
tWC
tAS
tAH
tCS
tCH
tCW
tOES
tOEH
tWP
tDS
tDH
tBLC
tLP
Parameter
Clock Frequency
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CEB Pulse Width
OEB High Setup Time
OEB High Hold Time
WEB Pulse Width
Data Setup Time
Data Hold Time
Byte Load Cycle
Last Byte Loaded to
Data Polling Output
Min
1
MAX
2
10
Units
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Write Mode (Note 1)
fc = 2 MHz (Note 1)
0
150
0
0
150
10
10
150
0
60
0.2
300
250
µs
µs
fc = 2 MHz
fc = 2 MHz
Note:
1.
Verified by functional testing.
Write Cycle
ADDRESS
t
AS
t
AH
t
WP
t
CH
t
BLC
t
WC
WE
t
CS
DATA
CE
t
OES
BYTE 0
t
CW
BYTE I
t
DS
t
DH
BYTE N
BYTE N
OE
PAGE LOAD
t
OEH
DATA Polling
Note: All or a portion of the 64 byte page may be loaded prior to writing, but the entire page is always written
with the contents of the data latches. Single byte data modification is not supported.
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