TRU050-SKLCA-12M2880000 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> TRU050-SKLCA-12M2880000

TRU050-SKLCA-12M2880000: DescriptionPhase Locked Loop, CDSO16; CategoryAnalog mixed-signal IC The signal circuit; File Size427KB，14 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

Download Datasheet Parametric View All

TRU050-SKLCA-12M2880000 Overview

Phase Locked Loop, CDSO16

TRU050-SKLCA-12M2880000 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	4017630405
package instruction	SMD-16
Reach Compliance Code	compliant
Country Of Origin	USA
YTEOL	5.9
Other features	SEATED HEIGHT CALCULATED
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDSO-G16
JESD-609 code	e0
length	20.32 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Maximum seat height	5.58 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	GULL WING
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.88 mm

Preview

Download Datasheet

View All

TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85° Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant Versions

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-based

PLL integrated circuit. It includes a digital phase

detector, op-amp, VCXO and additional integrated

functions for use in digital synchronization

applications. Loop filter software is available as well

SPICE models for circuit simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916

Page 1 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev:

4/12/2016

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.

DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about a

50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN

and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by

more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to produce

a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a block

diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does not

have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be centered

in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3

volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ

signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant

ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications

such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so

under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will not vary

signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary according

to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev:

4/12/2016

Recommended Resources

Circuit diagram for controlling charge and discharge of absorption capacitor

Delay circuit with multi-stage output

Crystal oscillator frequency multiplier circuit

Street light delay power saving switch circuit

6OXT(1.0) computer motherboard circuit diagram_22

820e computer motherboard circuit diagram_08

CCS Tips: Remove the prompt when burning DSP/BIOS: With the continuous development of digital signal processing theory and computers, modern industrial production and scientific and technological research need to rely on digital processing methods. Th...; 灞波儿奔 DSP and ARM Processors

SEED-DEC6416 is available for purchase, second-hand is also acceptable: Looking to buy 2 SEED-DEC6416 development boards, second-hand is also OK. If you have stock, please contact me on QQ: 466242178...; guoping2292 Buy&Sell

Calculation of stack usage in C2000 DSP: [size=4] For those who work on power electronics software, there is usually not much code in this line, and it often takes several months to adjust a few lines of code, such as grid-connected algorith...; 灞波儿奔 DSP and ARM Processors

IRLR024 Output Current: A 100W/200R cement resistor is connected to the J14 load. I checked the power meter and found that the load power is less than 1W. The voltage given by PC6 is 3.3V. The meter shows that there is a cur...; tangwei8802429 Analog electronics

Bidirectional thyristor circuit wiring problem: As shown in the figure, the wiring method of the bidirectional thyristor in the circuit is that because it is bidirectional, I swapped T2 and T1. The thyristor was always in the on state and could not...; 大威德su Switching Power Supply Study Group

"Goodbye 2019, Hello 2020" + The wind and clouds are free and happy: First of all, I wish you all a happy Chinese New Year. This year can actually be described as "turbulent". Electronic technology and chips have become the top search terms in 2019. Every fluctuation i...; 北方 Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components