5V19EE902NLGI datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> 5V19EE902NLGI

5V19EE902NLGI: DescriptionVFQFPN-32, Tray; Categorylogic logic; File Size504KB，35 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric Compare View All

5V19EE902NLGI Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	5V19EE902NLGI	-	-	View	Buy Now

5V19EE902NLGI Overview

VFQFPN-32, Tray

5V19EE902NLGI Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	VFQFPN
package instruction	HVQCCN,
Contacts	32
Manufacturer packaging code	NLG32P1
Reach Compliance Code	compli
ECCN code	EAR99
series	5V
Input adjustment	MUX
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	7
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	0.9 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	5 mm
minfmax	500 MHz
Base Number Matches	1

Preview

Download Datasheet

View All

DATASHEET

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

Description

The IDT5V19EE902 is a programmable clock generator

intended for high performance data-communications,

telecommunications, consumer, and networking

applications. There are four internal PLLs, each individually

programmable, allowing for four unique non-integer-related

frequencies. The frequencies are generated from a single

reference clock. The reference clock can come from one of

the two redundant clock inputs. Automatic or manual

switchover function allows any one of the redundant clocks

to be selected during normal operation.

The IDT5V19EE902 is in-system, programmable and can

be programmed through the use of I

C interface. An

internal EEPROM allows the user to save and restore the

configuration of the device without having to reprogram it on

power-up.

Each of the four PLLs has an 7-bit reference divider and a

12-bit feedback divider. This allows the user to generate

four unique non-integer-related frequencies. The PLL loop

bandwidth is programmable to allow the user to tailor the

PLL response to the application. For instance, the user can

tune the PLL parameters to minimize jitter generation or to

maximize jitter attenuation. Spread spectrum generation

and/or fractional divides are allowed on two of the PLLs.

There are a total of six 8-bit output dividers. Each output

bank can be configured to support LVTTL, LVPECL, LVDS

or HCSL logic levels. Out0 (Output 0) supports LVTTL

standard only. The outputs are connected to the PLLs via a

switch matrix. The switch matrix allows the user to route the

PLL outputs to any output bank. This feature can be used to

simplify and optimize the board layout. In addition, each

output's slew rate and enable/disable function is

programmable.

IDT5V19EE902

Features

•

Four internal PLLs

Internal non-volatile EEPROM

Fast (400kHz) mode I

C serial interface

Input frequency range: 1 MHz to 200 MHz

Output frequency range: 4.9 kHz to 500 MHz

Reference crystal input with programmable linear load

capacitance

– Crystal frequency range: 8 MHz to 50 MHz

•

Integrated VCXO

•

Four independently controlled VDDO (1.8V - 3.3V)

•

Each PLL has a 7-bit reference divider and a 12-bit

feedback-divider

•

8-bit output-divider blocks

•

Fractional division capability on one PLL

•

Two of the PLLs support spread spectrum generation

capability

•

I/O Standards:

– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS

– Outputs - LVPECL, LVDS and HCSL

– Inputs - 3.3 V LVTTL/ LVCMOS

•

Programmable slew rate control

Programmable loop bandwidth

Programmable output inversion to reduce bimodal jitter

Redundant clock inputs with auto and manual switchover

options

Individual output enable/disable

Power-down mode

3.3V core V

Available in VFQFPN package

-40 to +85 C Industrial Temp operation

IDT®

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

IDT5V19EE902

REV N 092412

5V19EE902NLGI Related Products

	5V19EE902NLGI	5V19EE902NLGI8
Description	VFQFPN-32, Tray	VFQFPN-32, Reel
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Parts packaging code	VFQFPN	VFQFPN
package instruction	HVQCCN,	HVQCCN,
Contacts	32	32
Manufacturer packaging code	NLG32P1	NLG32P1
Reach Compliance Code	compli	compliant
ECCN code	EAR99	EAR99
series	5V	5V
Input adjustment	MUX	MUX
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e3	e3
length	5 mm	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	32	32
Actual output times	7	7
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns	0.075 ns
Maximum seat height	0.9 mm	0.9 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	5 mm	5 mm
minfmax	500 MHz	500 MHz
Base Number Matches	1	1

Recommended Resources

Forward and reverse control circuit to prevent phase short circuit

High power factor electronic ballast circuit diagram

Using LM199 to form a standard power supply circuit diagram

amplitude demodulator

Simple stepless speed fan circuit

Computer motherboard circuit diagram 830_51

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components