Modes of Operation and Pin-outs ................................................................................................................................................ 6
Pin-out Top Views................................................................................................................................................................. 6
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ........................................................................................... 7
Frequency Stability ............................................................................................................................................................. 11
Output frequency and format .............................................................................................................................................. 11
Output Frequency Tuning ................................................................................................................................................... 11
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 12
Control Voltage Bandwidth ................................................................................................................................................. 15
Pull Range, Absolute Pull Range ............................................................................................................................................... 16
I
2
C Control Registers ................................................................................................................................................................. 21
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 21
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 22
Register Address: 0x02. DIGITAL PULL RANGE CONTROL ............................................................................................ 23
Register Address: 0x05. PULL-UP DRIVE STRENGTH CONTROL .................................................................................. 24
Register Address: 0x06. PULL-DOWN DRIVE STRENGTH CONTROL ............................................................................ 25
Serial Interface Configuration Description.................................................................................................................................. 26
Serial Signal Format .................................................................................................................................................................. 26
Parallel Signal Format................................................................................................................................................................ 27
Parallel Data Format .................................................................................................................................................................. 27
I
2
C Timing Specification ............................................................................................................................................................. 29
I
2
C Device Address Modes ........................................................................................................................................................ 30
Schematic Example ................................................................................................................................................................... 31
Dimensions and Patterns ........................................................................................................................................................... 32
Ordering Information .................................................................................................................................................................. 34
Rev 0.60
Page 2 of 36
www.sitime.com
SiT5157
60 to 220 MHz,
±0.5
ppm
Elite Platform™ Super-TCXO
Electrical Characteristics
PRELIMINARY
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd
Table 1. Output Characteristics
Parameters
Output Frequency Range
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Output Voltage Level
Frequency Stability over Temperature
Symbol
F
DC
Tr, Tf
VOH
VOL
V_out
F_stab
Min.
60.000001
45
–
90%
–
0.8
-0.5
-1.0
-2.5
Frequency vs. Temperature Slope
ΔF/ΔT
–
–
–
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
–
–
Initial Tolerance
Supply Voltage Sensitivity
Output Load Sensitivity
First Year Aging
Start-up Time
First Pulse Accuracy
F_init
F_vdd
F_load
F_1y
T_start
T_stability
-1
–
–
–
–
–
–
Typ.
–
–
1
–
–
–
–
–
–
±15
±25
±60
±0.13
±0.21
±0.5
–
±20
±10
±10
±1
5
10
Max.
220
55
–
–
10%
1.2
+0.5
+1.0
+2.5
–
–
–
–
–
–
+1
–
–
–
–
–
–
Unit
MHz
%
ns
Vdd
Vdd
V
ppm
ppm
ppm
ppb/°C
ppb/°C
ppb/°C
ppb/s
ppb/s
ppb/s
ppm
ppb
ppb
ppb
ppm
ms
ms
10% - 90% Vdd
I
OH
= -6 mA, (Vdd = 3.3 V, 3.0 V, 2.8 V, 2.5 V)
I
OL
= 6 mA, (Vdd = 3.3 V, 3.0 V, 2.8 V, 2.5 V)
Measured peak-to-peak swing at any Vdd
Referenced to (fmax + fmin)/2 over the specified
temperature range
See “Ordering Information” for frequency stability
ordering codes (K, A, D)
F_stab = ±0.5 ppm
F_stab = ±1 ppm
F_stab = ±2.5 ppm
F_stab = ±0.5 ppm , 0.5C/min temperature ramp rate
F_stab =
±1.0
ppm , 0.5C/min temperature ramp rate
F_stab =
±2.5
ppm , 0.5C/min temperature ramp rate
Initial frequency at 25°C inclusive of solder-down
shift at 48 hours after 2 reflows
Vdd ±5%
LVCMOS output, 15 pF ±10%
Clipped sinewave output, 10kΩ, 10 pF ±10%
At 25°C
Time to first pulse, measured from the time Vdd
reaches 90% of its final value
Time to first accurate pulse within rated stability,
measured from the time Vdd reaches 90% of its final
value
Condition
Frequency Coverage
LVCMOS Output Characteristics
Clipped Sinewave Output Characteristics
Frequency Stability - Stratum 3 Grade
Start-up Characteristics
Rev 0.60
Page 3 of 36
www.sitime.com
SiT5157
60 to 220 MHz,
±0.5
ppm
Elite Platform™ Super-TCXO
Table 2. DC Characteristics
Parameters
Supply Voltage
Symbol
Vdd
Min.
2.25
2.52
2.7
2.97
Current Consumption
OE Disable Current
Operating Temperature Range
IDD
I_od
T_use
–
–
-20
-40
-40
Typ.
2.5
2.8
3.0
3.3
Max.
2.75
3.08
3.3
3.63
PRELIMINARY
Unit
V
V
V
V
mA
mA
°C
°C
°C
Condition
Contact
SiTime
for 2.25V to 3.63V continuous supply
voltage support
Supply Voltage
Current Consumption
–
45
44.5
–
–
–
–
Temperature Range
+70
+85
+105
F = 98.304 MHz, No Load
OE = GND, output is weakly pulled down
Extended Commercial
Industrial. Contact
SiTime
for 105
°C
support
Extended Industrial
Table 3. Input Characteristics
Parameters
Input Impedance
Input High Voltage
Input Low Voltage
Pull Range
PR
Symbol
Z_in
VIH
VIL
Min.
–
70
–
Typ.
100
–
–
Max.
–
–
30
Unit
kΩ
%
%
Internal pull up to Vdd
Condition
Input Characteristics
–
OE Pin
Frequency Tuning Range – Voltage Control or I
2
C mode
±6.25, ±10, ±12.5, ±25, ±50,
±80, ±100, ±125, ±150, ±200,
±400, ±600, ±800, ±1200,
±1600, ±3200
90%
–
10
–
Positive
–
2
ppm
Voltage Control Characteristics
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Frequency Change Polarity
Pull Range Linearity
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Current High
Leakage in high impedance mode
Input Hysteresis
Input Capacitance
Rise Time
Fall Time
VIL
VIH
VOL
IOL
I_leak
V_hys
C_in
Tr
Tf
VC_U
VC_L
VC_z
VC_c
–
–
–
10
0.5
–
–
–
–
–
–
–
–
–
–
–
–
10%
–
–
–
0.3
–
0.4
–
24
0.4
0.3
3
120
60
75
Vdd
Vdd
MΩ
kHz
%
V
V
V
mA
µA
V
V
pF
ns
ns
ns
Vdd = 3.3V, 30% to 70%
Vdd = 2.5V, 30% to 70%
0.1 Vdd< VOUT < 0.9 Vdd
Vdd = 3.3V
Vdd = 2.5V
Contact
SiTime
for other input bandwidth options
I C Interface Characteristics, 1 MHz, 200 Ohm, 550 pF (Max I
2
C Bus Load)
–
0.7
–
21
5.5
0.2
0.2
–
–
30
40
Rev 0.60
Page 4 of 36
www.sitime.com
SiT5157
60 to 220 MHz,
±0.5
ppm
Elite Platform™ Super-TCXO
Table 4. Jitter & Phase Noise
Parameters
RMS Phase Jitter (random)
Spurs
RMS Period Jitter
Peak Cycle-to-Cycle Jitter
1 Hz offset
10 Hz offset
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
5 MHz offset
T_jitt
T_jitt_cc
Symbol
Min.
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
0.30
0.30
-94
2
10
-54
-82
-104
-126
-132
-135
-149
-155
Max.
Jitter
T_phj
–
–
–
–
–
Phase Noise
–
–
–
–
–
–
–
–
PRELIMINARY
Unit
ps
ps
dBc
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Condition
f = 98.304 MHz, Integration bandwidth = 12 kHz to 20 MHz
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz
f = 98.304 MHz, 12 kHz to 5 MHz offsets
f = 98.304 MHz per JESD65 standard
f = 98.304 MHz per JESD65 standard
f = 98.304 MHz, TCXO and DCTCXO modes, and
VCTCXO mode with ±6.25 ppm pull range
Table 5. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Continuous Power Supply Voltage Range (Vdd)
Human Body Model (HBM) ESD Protection
Soldering Temperature (follow standard Pb-free
soldering guidelines)
Junction Temperature
[1]
Note:
1. Exceeding this temperature for an extended period of time may damage the device.
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