V59C1512804QEF19AH datasheet, PDF

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V59C1512804QEF19AH: DescriptionDDR DRAM, 64MX8, 0.35ns, CMOS, PBGA60,; Categorystorage storage; File Size2MB，73 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V59C1512804QEF19AH Overview

DDR DRAM, 64MX8, 0.35ns, CMOS, PBGA60,

V59C1512804QEF19AH Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	114798062
package instruction	FBGA, BGA60,9X11,32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	0.35 ns
Maximum clock frequency (fCLK)	533 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B60
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	8
Number of terminals	60
word count	67108864 words
character code	64000000
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	64MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA60,9X11,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Continuous burst length	4,8
Maximum standby current	0.02 A
Maximum slew rate	0.225 mA
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

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V59C1512(804/164)QE

HIGH PERFORMANCE 512 Mbit DDR2 SDRAM

4 BANKS X 16Mbit X 8 (804)

4 BANKS X 8Mbit X 16 (164)

DDR2-533

Clock Cycle Time (t

CK3

)

Clock Cycle Time (t

CK4

)

Clock Cycle Time (t

CK5

)

Clock Cycle Time (t

CK6

)

Clock Cycle Time (t

CK7

)

System Frequency (f

CK max

)

5ns

3.75ns

266 MHz

DDR2-667

5ns

3.75ns

3ns

333 MHz

25A

DDR2-800

5ns

3.75ns

3ns

2.5ns

400 MHz

DDR2-800

5ns

3.75ns

2.5ns

400 MHz

PRELIMINARY

19A

DDR2-1066

5ns

3.75ns

2.5ns

1.87ns

533 MHz

Features

Description

The V59C1512(804/164)QE is a four bank DDR DRAM

organized as 4 banks x 16Mbit x 8 (804) or 4 banks x 8Mbit

x 16 (164). The V59C1512(804/164)QE achieves high

speed data transfer rates by employing a chip architec-

ture that prefetches multiple bits and then synchronizes

the output data to a system clock.

The chip is designed to comply with the following key

DDR2 SDRAM features:(1) posted CAS with additive la-

tency, (2) write latency = read latency -1, (3) On Die Ter-

mination.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

s are synchronized with a pair of bidirectional strobes

(DQS, DQS) in a source synchronous fashion.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Available Speed Grade:

-37 (DDR2-533) @ CL 4-4-4

-3 (DDR2-667) @ CL 5-5-5

-25A (DDR2-800) @ CL 6-6-6

-25 (DDR2-800) @ CL 5-5-5

-19A(DDR2-1066)@CL 7-7-7

High speed data transfer rates with system frequency

up to 533MHz

Posted CAS

Programmable CAS Latency: 3, 4, 5, 6 and 7

Programmable Additive Latency:0, 1, 2, 3, 4, 5 and 6

Write Latency = Read Latency -1

Programmable Wrap Sequence: Sequential

or Interleave

Programmable Burst Length: 4 and 8

Automatic and Controlled Precharge Command

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 7.8 us at lower than Tcase 85

3.9 us at 85

C < Tcase

≤

ODT (On-Die Termination)

Weak Strength Data-Output Driver Option

Bidirectional differential Data Strobe (Single-ended

data-strobe is an optional feature)

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

Differential clock inputs CK and CK

JEDEC Power Supply 1.8V ± 0.1V

Available in 60-ball FBGA for x8 component or 84 ball

FBGA for x16 component

All inputs & outputs are compatible with SSTL_18 in-

terface

tRAS lockout supported

Read Data Strobe supported (x8 only)

Internal four bank operations with single pulsed RAS

Device Usage Chart

Operating

Temperature

Range

0°C

≤

95°C

-40°C

≤

95°C

-40°C

≤

105°C

V59C1512(804/164)QE Rev. 1.2 January 2015

Package Outline

60 ball FBGA

84 ball FBGA

•

CK Cycle Time (ns)

-37

•

Power

-19A

•

-3

•

-25A

•

-25

•

Std.

•

Temperature

Mark

Blank

ProMOS TECHNOLOGIES

V59C1512(804/164)QE

Signal Pin Description

CK, CK

CKE

RAS, CAS, WE

A0 - A13

Type

Input

Function

The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CK.

Activates the CK signal when high and deactivates the CK signal when low, thereby initiates either the

Power Down mode, or the Self Refresh mode.

CS enables the command decoder when low and disables the command decoder when high. When

the command decoder is disabled, new commands are ignored but previous operations continue.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be

executed by the SDRAM.

During a Bank Activate command cycle, A0-A13 defines the row address ( RA0-RA13 ) when sampled

at the rising clock edge for x8 and A0-A12 row address for x16 device.

During a Read or Write command cycle, A0-An defines the column address ( CA0-CAn ) when sampled

at the rising clock edge.CAn depends on the SDRAM organization:

64M x 8 DDR CAn = CA9

32M x 16 DDR CAn = CA9

In addition to the column address, A10 ( = AP ) is used to invoke autoprecharge operation at the end

of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the

bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10 ( = AP ) is used in conjunction with BA0 and BA1 to control

which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless

of state of BA0 and BA1.

BA0, BA1

DQx

DQS, (DQS)

LDQS, (LDQS)

UDQS, (UDQS)

RDQS, (RDQS)

Input

Input/

Output

Input/

Output

Selects which bank is to be active.

Data Input/Output pins operate in the same manner as on conventional DRAMs.

DQ0-DQ7 for x8 component and DQ0-DQ15 for x16 component.

Data Strobe, output with read data, input with write data. Edge-aligned with read data, centered in write

data. For x16 device, LDQS corresponds to the data on DQ0-DQ7; UDQS coresponds to the data on

DQ8-DQ15. For x8 device, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify

read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or

paired with optional complimentary signals DQS, LDQS, UDQS, and RDQS to provide differential pair

signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all

complementary data strobe signals.

In this data sheet, “differential DQS signals” refers to any of the following with A10 = 0 of EMRS(1)

x8 DQS/DQS if EMRS(1)[A11] = 0

x8 DQS/DQS, RDQS/RDQS if EMRS(1)[A11] = 1

x16 LDQS/LDQS and UDQS/UDQS

“single-ended DQS signals” refers to any of the following with A10 = 1 of EMRS(1)

x8 DQS if EMRS(1)[A11] = 0

x8 DQS, RDQS, if EMRS(1)[A11] = 1

x16LDQS and UDQS

V59C1512(804/164)QE Rev. 1.2 January 2015

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