C1812A561G2GAL7246 datasheet, PDF

Datasheet> All Categories > Passive components> capacitor> C1812A561G2GAL7246

C1812A561G2GAL7246: DescriptionCeramic Capacitor, Ceramic, 200V, 2% +Tol, 2% -Tol, C0G, -/+30ppm/Cel TC, 0.00056uF, 1812,; CategoryPassive components capacitor; File Size1MB，8 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com

Download Datasheet Parametric View All

C1812A561G2GAL7246 Overview

Ceramic Capacitor, Ceramic, 200V, 2% +Tol, 2% -Tol, C0G, -/+30ppm/Cel TC, 0.00056uF, 1812,

C1812A561G2GAL7246 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	709417549
package instruction	, 1812
Reach Compliance Code	not_compliant
ECCN code	EAR99
YTEOL	6.62
capacitance	0.00056 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	2.03 mm
JESD-609 code	e0
length	4.57 mm
negative tolerance	2%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
method of packing	Bulk
positive tolerance	2%
Rated (DC) voltage (URdc)	200 V
series	C(SIZE)A
size code	1812
Temperature characteristic code	C0G
Temperature Coefficient	30ppm/Cel ppm/°C
Terminal surface	Tin/Lead (Sn70Pb30) - with Nickel (Ni) barrier
width	3.18 mm

Preview

Download Datasheet

View All

CERAMIC HIGH RELIABILITY

GENERAL INFORMATION GR900 SERIES

HIGH RELIABILITY — GR900

/ Q-SPEC

GR900 capacitors are intended for use in any application where the

chance of failure must be reduced to the lowest possible level. While

any well-made multilayer ceramic capacitor is an inherently reliable

device, GR900 capacitors receive special attention in all phases of

manufacture including:

•

Raw Materials Selection

•

Clean Room Production

•

Individual Batch Testing

•

C-SAM (when applicable)

•

Singular Batch Identity is Maintained

•

Destructive Physical Analysis

•

These parts are well worth the added investment in comparison to the

cost of a device or system failure.

Typical applications include: Medical, Aerospace, Communication

Satellites, Radar and Guidance Systems.

SCREENING AND SAMPLE TESTS

Each batch receives the following testing/inspections:

In Process Inspection (Per MIL-PRF-123):

100% Visual Inspection.

Destructive Physical Analysis: (DPA) - A sample is pulled from

each lot and examined per EIA-469 and KEMET’s strict internal

void and delamination criteria. Sampling plan is per MIL-PRF-123.

C-SAM (GR900 / “A” in the fifth character position of the ordering

code): May be performed on batches failing to meet the DPA

criteria for removal of marginal product. Not required on each lot.

C-SAM (Q-SPEC / “Q” in the fifth character position of the ordering

code): Receive 100% C-SAM of lot prior to application of end

metallization.

Group A

1. Thermal Shock:

Materials used in the construction of multilayer

ceramic capacitors possess various thermal coefficients of expansion.

To assure maximum uniformity, each part is temperature cycled in

accordance to MIL-STD-202, Method 107, Condition A with Step 3

being 125°C. Number of cycles shall be 20 (100% of lot).

2. Voltage Conditioning:

One of the most strenuous environments for

any capacitor is the high temperature/high voltage test. All units are

subject to twice-rated voltage to the units at the maximum rated

temperature of 125°C for a minimum of 168 hours and a maximum of

264 hours. The voltage conditioning may be terminated at any time

during 168 hours to 264 hours time interval that confirmed failures meet

the requirements of the PDA during the last 48 hours of 1 unit or .4%

(100% of lot).

Optional Voltage Conditioning (Accelerated Voltage

Conditioning):

All conditions of the standard voltage conditioning

apply with the exception of increased voltage and decreased test time.

Refer to MIL-PRF-123 for the proper formula.

*Step 5 is performed on chips at this point (100% of lot).

3. Dielectric Withstanding Voltage:

250% of the DC rated voltage at

25°C (100% of lot).

9. Percent Defective Allowable (PDA):

The overall PDA is 8% for

parts outside the MIL-PRF-123 values. The PDA is per MIL-PRF-

123 for all parts that are valid MIL-PRF-123 values. The PD

includes steps 1 through 8 above with the following exceptions.

Capacitance exclusion - capacitance values no more than 5% or

.5pF, whichever is greater for BX characteristic or 1% or .3pF,

whichever is greater for BP characteristic beyond specified

tolerance limit, shall be removed from the lot but shall not be

considered defective for determination of the PD.

Insulation Resistance at 25°C — Product which is not acceptable

for twice the military limit but is acceptable per the military limit, is

removed from the lot but shall not be considered defective for

determination of the PD.

10. Visual and Mechanical Examination:

Performed per MIL-

PRF-123 criteria.

11. Radiographic Examination (Leaded Devices Only):

Radial

devices receive a one-plane X-ray.

12. Destructive Physical Analysis (DPA):

A sample is examined

on each lot per EIA-469. Sampling Plan is per MIL-PRF-123.

STANDARD PACKAGING

All products are packaged in trays except C512 capacitors which

are packaged 1 piece per bag.

*Note: All packaging is ESD protected.

DATA PACKAGE

A data package is sent with each shipment which contains:

1. Final Destructive Physical Analysis (DPA) report.

2. Certificate of Compliance stating that the parts meet all

applicable requirements of the appropriate military specification to

the best failure level to which KEMET is approved.

3. Summary of Group A Testing.

Group B

MIL-PRF-123 Group B testing is available with special order.

Please contact KEMET for additional information and ordering

details.

4. Insulation Resistance:

The 25°C measurement with rated

voltage applied shall be the lesser of 100 GΩ or 1000 Megohm -

Microfarads (100% of lot).

*5. Insulation Resistance:

The 125°C measurement with rated

voltage applied shall be the lesser of 10 GΩ or 100 Megohm -

Microfarads (100% of lot). For chips, 125°C IR is performed prior to

Step 3 above.

6. Storage

at 150°C for 2 hours minimum without voltage applied

followed by a 12-hour minimum stabilization period (temperature

characteristic BX only).

7. Capacitance:

Shall be within specified tolerance at 25°C (100%

of lot). (Aging phenomenon is taken into account for BX dielectric

to obtain capacitance.)

8. Dissipation Factor:

Shall not exceed 2.5% for X7R (BX)

dielectric, 0.15% for C0G (BP) dielectric at 25°C. (100% of lot.)

Recommended Resources

Phone doorbell circuit

One person operates the line number circuit 02

Simple stepless speed regulator circuit

Medical sensing ISO107 isolation amplifier circuit

Voltage regulator circuit diagram to expand output voltage range a

555 light-controlled automatic timing energy-saving street light

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components