P
RODUCT
S
PECIFICATION
1
Z90102/103/104
40-P
IN
L
OW
-C
OST
D
IGITAL
T
ELEVISION
C
ONTROLLER
FEATURES
8-Bit CMOS Microcontroller for Consumer
Television, Cable and Satellite Receiver Ap-
plications.
Device
Z90102
Z90103
Z90104
ROM
(KB)
4
6
8
RAM*
(Bytes)
236
236
236
I/O
24
24
24
s
s
1
Clock Speed up to 4 MHz
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC or External Clock Drive
Permanently Enabled
Watch-Dog/Power-On Reset Timer
3K x 6-Bit Character Generator ROM
120 x 7-Bit Video RAM
Mask Programmable 96-Character Set Display. The
90102 and 90103 6-Row x 20 Column Format, 12x15
Pixel Character Cell. The 90104 8-Row x 20 Column
Format 12x15 Pixel Character Cell. The 90102, 90103
90104 Capable of supporting English, Korean, Thai,
Chinese and Japanese High Resolution Characters.
Fully Programmable Color Attributes Including Row
Character,
Row
Background/Fringes,
Frame
Background/Position, Bar Graph Color Change, and
Character Size.
Programmable Display Position and Character Size
Control
One Pulse Width Modulator (14-Bit Resolution) for
Voltage Synthesis Tuner Control.
Three Pulse Width Modulator (8-Bit Resolution) for
Picture Control
Three Pulse Width Modulators (6-Bit Resolution) for
Audio Control
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Note:
*General-Purpose
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Lowest Cost DTC Family Member
Low Power Consumption
Fast Instruction Pointer - 1.5
m
s @ 4 MHz
Two Standby Modes - STOP and HALT
Low Voltage Detection/Voltage Sensitive Reset
Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input,
3-Bit Output) Register Mapped Ports
Port 6 (6-Bit Input and Tristate Comparator AFC Input)
Memory Mapped I/O Ports
All Digital CMOS Levels Schmitt-Triggered
Two Programmable 8-Bit Counter/Timers each with 6-
Bit Programmable Prescaler.
Six Vectored, Priority Interrupts from Six Different
Sources
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GENERAL DESCRIPTION
The Z90102/3/4 40-pin Low-Cost Digital Television Con-
troller are members of the Z8
®
STOP Mode MCU single-
chip family with 4, 6, and 8 KB of ROM and 236 bytes of
RAM. The device is offered in a 40-pin package and is
DS97TEL1902
CMOS compatible. The DTC offers mask programmed
ROM which enables the Z8
®
MCU to be used in a high vol-
ume production application device embedded with a cus-
tom program (customer supplied program) and combines
1
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
GENERAL DESCRIPTION
(Continued)
together with the Z86C27 and Z86127 to provide support
for mid range and low end TV applications.
Zilog’s DTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation ca-
pabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The de-
vice provides an ideal performance and reliability solution
for consumer and industrial television applications.
The Z90102/3/4 architecture is characterized by utilizing
Zilog’s advanced Superintegration™ design methodology.
The device has an 8-bit internal data path controlled by a
Z8 microcontroller and On Screen Display (OSD) logic cir-
cuits and Pulse Width Modulators (PWM). On-chip periph-
erals include two register mapped I/O ports (Ports 2 and
3), interrupt control logic (one software, two external and
three internal interrupts) and a standby mode recovery in-
put port (Port 3, P30).
The OSD control circuits support 6 rows x 20 columns of
characters. The character color is specified by row. One of
the six rows is assigned to show two kinds of colors for bar
type displays such as volume control. The OSD is capable
of displaying either low resolution (5 x 7 dot pattern) or high
resolution (11 x 15 dot pattern) characters.
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Three 8-
bit PWM ports used to vary picture levels.
For DTC applications demanding powerful I/O capabili-
ties, the Z90102/3/4 fulfills this with 24 I/O pins dedicated
to input and output. These lines are grouped into three
ports, and are configurable under software control to pro-
vide timing, status signals, parallel I/O and an address/da-
ta bus for interfacing to external memory.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general-purpose registers, two I/O Port regis-
ters, 15 control and status registers and three reserved
registers.
To unburden the program from coping with the real-time
problems such as counting/timing and data communica-
tion, the DTC offers two on-chip counter/timers with a large
number of user selectable modes (Figure 1).
Notes:
All signals with a preceding front slash, "/", are ac-
tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
2
DS97TEL1902
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