M393B2873DZ1-CH9 datasheet, PDF

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M393B2873DZ1-CH9: DescriptionDDR DRAM Module, 128MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size1MB，64 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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M393B2873DZ1-CH9 Overview

DDR DRAM Module, 128MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240

M393B2873DZ1-CH9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1873292511
Parts packaging code	DIMM
package instruction	DIMM, DIMM240,40
Contacts	240
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Humidity sensitivity level	3
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.578 A
Maximum slew rate	4.255 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL

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Registered DIMM

DDR3 SDRAM

DDR3 SDRAM Specification

240pin Registered DIMM based on 1Gb D-die

72-bit ECC

82FBGA with Lead-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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Rev. 1.1 August 2008

Registered DIMM

Table Contents

DDR3 SDRAM

1.0 DDR3 Registered DIMM Ordering Information .......................................................................................................... 5

2.0 Key Features ................................................................................................................................................................ 5

3.0 Address Configuration ................................................................................................................................................ 5

4.0 Registered DIMM Pin Configurations (Front side/Back side) .................................................................................. 6

5.0 Pin Description ............................................................................................................................................................. 7

6.0 ON DIMM Thermal Sensor ........................................................................................................................................... 7

7.0 Input/Output Functional Description ......................................................................................................................... 8

8.0 Pinout comparison Based on Module Type .............................................................................................................. 9

9.0 Registering Clock Driver Specification .................................................................................................................... 10

9.1 Timing & Capacitance values ............................................................................................................................. 10

9.2 Clock driver Characteristics ............................................................................................................................... 10

10.0 Functional Block Diagram: ..................................................................................................................................... 11

10.1 1GB, 128Mx72 Module(Populated as 1 rank of x8 DDR3 SDRAMs) .............................................................. 11

10.2 2GB, 256Mx72 Module(Populated as 2 rank of x8 DDR3 SDRAMs) .............................................................. 12

10.3 2GB, 256Mx72 Module(Populated as 1 ranks of x4 DDR3 SDRAMs) ............................................................ 13

10.4 4GB, 512Mx72 Module(Populated as 2 ranks of x4 DDR3 SDRAMs) ............................................................ 14

10.5 4GB, 512Mx72 Module(Populated as 4 ranks of x8 DDR3 SDRAMs) ............................................................ 16

10.6 8GB,1Gx72 Module(Populated as 4 ranks of x4 DDR3 SDRAMs) .................................................................. 17

11.0 Absolute Maximum Ratings .................................................................................................................................... 22

11.1 Absolute Maximum DC Ratings ........................................................................................................................ 22

11.2 DRAM Component Operating Temperature Range ......................................................................................... 22

12.0 AC & DC Operating Conditions .............................................................................................................................. 22

12.1 Recommended DC Operating Conditions (SSTL - 15) .................................................................................... 22

13.0 AC & DC Input Measurement Levels ...................................................................................................................... 23

13.1 AC and DC Logic Input Levels for Single-ended Signals ............................................................................... 23

13.2 V

REF

Tolerances. ................................................................................................................................................ 24

13.3 AC and DC Logic Input Levels for Differential Signals .................................................................................. 25

13.3.1 Differential Signals Definition ................................................................................................................. 25

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .................................. 25

13.3.3 Single-ended Requirements for Differential Signals ............................................................................ 26

13.3.4 Differential Input Cross Point Voltage ................................................................................................... 27

13.4 Slew Rate Definition for Single Ended Input Signals ..................................................................................... 27

13.5 Slew rate definition for Differential Input Signals ........................................................................................... 27

14.0 AC and DC Output Measurement Levels ............................................................................................................... 28

14.1 Single Ended AC and DC Output Levels ......................................................................................................... 28

14.2 Differential AC and DC Output Levels ............................................................................................................. 28

14.3 Single Ended Output Slew Rate ....................................................................................................................... 28

14.4 Differential Output Slew Rate ........................................................................................................................... 29

15.0 IDD specification definition ..................................................................................................................................... 30

15.1 IDD SPEC Table .................................................................................................................................................. 32

16.0 Input/Output Capacitance ....................................................................................................................................... 35

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Registered DIMM

DDR3 SDRAM

17.0 Electrical Characteristics and AC timing ............................................................................................................... 36

17.1 Refresh Parameters by Device Density .......................................................................................................... 36

17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ....................................................... 36

17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ........................................................ 37

17.3.1 Speed Bin Table Notes ........................................................................................................................... 38

18.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333 ........................................................................... 39

18.1 Jitter Notes ........................................................................................................................................................ 42

18.2 Timing Parameter Notes ................................................................................................................................... 43

18.3 Address / Command Setup, Hold and Derating: ............................................................................................ 44

18.4 Data Setup, Hold and Slew Rate Derating: ..................................................................................................... 50

19.0 Physical Dimensions : ............................................................................................................................................ 55

19.1 128Mbx8 based 128Mx72 Module(1 Rank) ..................................................................................................... 55

19.1.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs ................................................... 55

19.2 128Mbx8 based 256Mx72 Module(2 Ranks) ................................................................................................... 56

19.2.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs ................................................... 56

19.3 256Mbx4 based 256Mx72 Module(1 Ranks) ................................................................................................... 57

19.3.1 x72 DIMM, populated as one physical ranks of x4 DDR3 SDRAMs ................................................... 57

19.4 256Mbx4 based 512Mx72 Module(2 Ranks) ................................................................................................... 58

19.4.1 x72 DIMM, populated as one physical ranks of x4 DDR3 SDRAMs ................................................... 58

19.4.2 Heat Spreader Design Guide ................................................................................................................ 59

19.5 128Mbx8 based 512Mx72 Module(4 Ranks)................................................................................................... 61

19.5.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs ................................................... 61

19.6 8GB based 1Gx72 Module(4 Ranks) ............................................................................................................... 62

19.6.1 x72 DIMM, populated as one physical ranks of x8 DDR3 SDRAMs ................................................... 62

19.6.2 Heat Spreader Design Guide ................................................................................................................ 63

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Rev. 1.1 August 2008

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