M62354P/FP/GP
8-bit 6ch D/A Converter with Buffer Amplifiers
REJ03D0872-0300
Rev.3.00
Mar 25, 2008
Description
The M62354 is an integrated circuit semiconductor of CMOS structured with 6 channels of built-in D/A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer format of digital data to allow connection with
microcomputer with minimum wiring.
It is able to cascading serial use with DO terminal.
The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both
input/output.
Features
•
12-bit serial data input (3-wire serial data transfer method)
•
Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
V
CC
14
V
DD
13
A
O6
12
A
O5
11
A
O4
10
A
O3
9
V
SS
8
Buffer
OP Amp
+
−
+
−
+
−
D/A
Ch6
5
D/A
4
D/A
8-bit R-2R
segment
D/A converter
3
L
(6)
......
Address
decoder
L
L
L
Ch1
2
D/A
D11 10 9 8 D7 6 5 4 3 2 1 0
8-bit R-2R
segment
D/A converter
+
−
12-bit shift register
+
−
+
−
8-bit
latch
(6)
....
8-bit
latch
Buffer
OP Amp
1
2
3
4
5
6
7
DO
LD
CLK
DI
A
O1
A
O2
GND
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 1 of 9
M62354P/FP/GP
Pin Arrangement
M62354P/FP
DO
LD
CLK
DI
A
O1
A
O2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
M62354GP
V
CC
V
DD
A
O6
A
O5
A
O4
A
O3
V
SS
DO
LD
CLK
DI
A
O1
A
O2
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
DD
A
O6
A
O5
A
O4
A
O3
NC
V
SS
NC: No connection
(Top view)
Outline: 14P4
PRSP0014DD-A (14P2N-A)
(Top view)
Outline: PLSP0016JA-A (16P2E-A)
Pin Description
Pin No.
4 (4)
1 (1)
3 (3)
2 (2)
5 (5)
6 (6)
9 (11)
10 (12)
11 (13)
12 (14)
14 (16)
7 (8)
13 (15)
8 (9)
Note:
Pin Name
DI
DO
CLK
LD
A
O1
A
O2
A
O3
A
O4
A
O5
A
O6
V
CC
GND
V
DD
V
SS
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
LD terminal input high level then latch circuit data load
8-bit D/A converter output terminal
Power supply terminal
Digital and analog common GND
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
( ) : M62354GP
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 2 of 9
M62354P/FP/GP
Block Diagram for Explanation of Terminals
V
CC
14
GND
7
DI
4
CLK
3
12-bit shift register
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
1
DO
(8)
(6)
Address decoder
1 2 3 4 5 6
2
LD
D0
1
.....
8-bit
latch
D7
D0
...............................
6
...............................
.....
8-bit
latch
D7
8-bit
R-2R segment
D/A converter
8-bit
R-2R segment
D/A converter
+
−
+
−
.........................................
13
5
12
8
A
O1
V
DD
(VrefU)
A
O6
V
SS
(VrefL)
Absolute Maximum Ratings
Item
Supply voltage
D/A converter upper reference voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
V
CC
V
DD
V
IN
V
O
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to V
CC
+ 0.3
–0.3 to V
CC
+ 0.3
440 (P) / 250 (FP) / 150 (GP)
–20 to +85
–40 to +125
Unit
V
V
V
V
mW
°C
°C
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 3 of 9
M62354P/FP/GP
Electrical Characteristics
<Digital Part>
(V
CC
, VrefU = 5 V
±
10%, V
CC
≥
VrefU, GND, VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.)
Item
Supply voltage
Circuit current
Input leak current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Symbol
V
CC
I
CC
I
ILK
V
IL
V
IH
V
OL
V
OH
Min
4.5
—
–10
—
0.8 V
CC
—
V
CC
– 0.4
Limits
Typ
5.0
0.7
—
—
—
—
—
Max
5.5
2.5
10
0.2 V
CC
—
0.4
—
Unit
V
mA
µA
V
V
V
V
Conditions
CLK = 1 MHz operation
V
CC
= 5 V, I
AO
= 0
µA
V
IN
= 0 to V
CC
I
OL
= 2.5 mA
I
OH
= –400
µA
<Analog Part>
(V
CC
, VrefU = 5 V
±
10%, V
CC
≥
VrefU, Ta = –20 to +85°C, unless otherwise noted.)
Item
Current dissipation
D/A converter upper
reference voltage range
D/A converter lower
reference voltage range
Buffer amplifier output
voltage range
Buffer amplifier output
drive range
Differential nonlinearity
error
Nonlinearity error
Zero code error
Full scale error
Output capacitive load
Buffer amplifier output
impedance
Symbol
I
DD
V
DD
V
SS
V
AO
I
AO
S
DL
S
L
S
ZERO
S
FULL
C
O
R
O
Min
—
3.5
Limits
Typ
0.7
—
Max
1.3
V
CC
V
CC
– 3.5
V
CC
– 0.1
V
CC
– 0.2
1
1.0
1.5
2
2
0.1
—
Unit
mA
V
Conditions
VrefU = 5 V, VrefL = 0 V
Data condition: at maximum current
The output does not necessarily be
the value within the reference voltage
setting range. The output value is
determined by the buffer amplifier
output voltage range (V
AO
).
I
AO
=
±
100
µA
I
AO
=
±
500
µA
Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
VrefU = 4.79 V
VrefL = 0.95 V
V
CC
= 5.5 V (15 mV/LSB)
Without load (I
AO
=
±0 µA)
GND
—
V
0.1
0.2
–1
–1.0
–1.5
–2
–2
—
—
—
—
—
—
—
—
—
—
5
V
mA
LSB
LSB
LSB
LSB
µF
Ω
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 4 of 9
M62354P/FP/GP
AC Characteristics
(V
CC
, VrefU = 5 V
±
10%, V
CC
≥
VrefU, GND, VrefL = 0 V, Ta = –20 to +85°C, unless otherwise noted.)
Item
Clock "L" pulse width
Clock "H" pulse width
Clock rise time
Clock fall time
Data setup time
Data hold time
LD setup time
LD hold time
LD "H" pulse width
Data output delay time
D/A output setting time
Symbol
t
CKL
t
CKH
t
CR
t
CF
t
DCH
t
CHD
t
CHL
t
LDC
t
LDH
t
DO
t
LDD
Min
200
200
—
—
30
60
200
100
100
70
—
Limits
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
200
200
—
—
—
—
—
350
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Conditions
C
L
≤
100 pF
C
L
≤
100 pF, V
AO
: 0.5
↔
4.5 V
The time until the output becomes
the final value of 1/2 LSB
Timing Chart
t
CR
t
CKH
t
CF
CLK
t
CKL
DI
t
LDH
t
DCH
t
CHD
t
CHL
t
LDC
LD
t
LDD
D/A output
t
DO
DO output
REJ03D0872-0300 Rev.3.00 Mar 25, 2008
Page 5 of 9
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