Preliminary Technical Data
FEATURES
Integrated Stereo Modulator & Power Stage
0.005% THD+N
101.5dB Dynamic Range
PSRR > 65 dB
R
DS-ON
< 0.3
Ω
(per transistor)
Efficiency > 80% @ 5W/6
Ω
EMI Optimized Modulator
On-Off-Mute Pop Noise Suppression
Short Circuit Protection
Over-Temperature Protection
Low Cost DMOS Process
Class-D Audio Power Amplifier
AD1990/AD1992/AD1994/AD1996
GENERAL DESCRIPTION
The AD199x is a two channel Bridge Tied Load (BTL)
switching audio power amplifier with integrated
∑
∆
modulator.
The modulator accepts a 1Vrms input signal (maximum power)
and generates a switching waveform to drive speakers directly.
One of the two modulators can control both output stages
providing twice the current for single-channel applications. A
digital, microcontroller-compatible interface provides control of
reset, mute and PGA gain as well as output signals for thermal
and over-current error conditions. The output stage can operate
from supply voltages ranging from 8V to 20V. The analog
modulator and digital logic operate from a 5V supply.
AD1990: 5Wx2 (10Wx1)
AD1992: 10Wx2 (20Wx1)
AD1994: 25Wx2 (50Wx1)
AD1996: 40Wx2 (80Wx1)
APPLICATIONS
Flat Panel Televisions
Automotive Amplifiers
PC Audio Systems
Mini Components
PGA0
PGA1
NFR+
50
AINR
NFL+
62
NFL-
63
32
31
60
53
LEFT CHANNEL
PVDD
7,8
4,5,6
NFR-
51
AINL
RIGHT CHANNEL
PVDD2
DRIVER
HIGH SIDE
41,42
PVDD2
43,44,45
OUTL+
1,2,3
OUTR+
LEVEL
SHIFT
+
DEAD
TIME
CONTROL
PGND1
PVDD1
OUTL-
9,10
MODULATOR
Σ∆
PGA
PGA
MODULATOR
Σ∆
11,12,13
DRIVER
HIGH SIDE
DRIVER
LOW SIDE
LEVEL
SHIFT
+
DEAD
TIME
CONTROL
DRIVER
LOW SIDE
PGND2
PVDD2
46,47,48
PGND2
39,40
DRIVER
HIGH SIDE
DRIVER
LOW SIDE
PVDD2
36,37,38
OUTR-
PGND1
PGND2
33,34,35
14,15,16
PGND1
PGND2
REF_FILT
AVDD
55
Ø1
VOLTAGE
REFERENCE
Ø2
Ø1
Ø2
57
56
AGND
DVDD
DGND
24,25
23,26
TEMPERATURE
SENSE &
OVER-CURRENT
PROTECTION
OSCILLATOR
MODE CONTROL LOGIC
MUTE/
POP
CONTROL
27
RST/PW DN
Figure 1. Block Diagram
Rev. PrA – 1/20/05
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
DCTRL0
DCTRL1
DCTRL2
ERR0
ERR1
MUTE
ERR2
MONO
CLKI
28
30
29
19
18
17
49
22
21
20
CLKO
AD199x
Preliminary Technical Data
TABLE OF CONTENTS
General Description
........................................................................ 1
AD199x—Specifications.................................................................. 3
test conditions unless otherwise noted...................................... 3
Absolute Maximum Ratings............................................................ 6
Pin Configurations And Functional Descriptions ....................... 7
Typical Performance Characteristics ............................................. 8
Functional Description.................................................................. 10
Device Architecture ................................................................... 10
Amplifier Gain............................................................................ 10
System Design............................................................................. 11
Outline Dimensions ....................................................................... 14
ESD Caution................................................................................ 14
Rev. PrA – 1/20/05 | Page 2 of 16
Preliminary Technical Data
AD199X—SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages
AV
DD
DV
DD
PV
DDX
Ambient Temperature
Load Impedance
Clock Frequency
Measurement Bandwidth
5V
5V
12 V
25 °C
6
Ω
11.2896 MHz
20 Hz to 20 KHz
AD199x
Table 1. Performance of both channels is identical
Parameter
OUTPUT POWER (P
O
)
AD1990
AD1992
AD1994
AD1996
Efficiency
R
ON
per High Side Transistor
per Low Side Transistor
Maximum Current Through OUTx
Thermal Warning Active
Thermal Shutdown Active
Overcurrent Shutdown Active
Nominal Input Level
Modulation Factor
PERFORMANCE SPECIFICATIONS
Total Harmonic Distortion (THD+N)
Min
Typ
4
5
8
10
16
25
25
40
84
0.3
0.2
4
135
150
4
1.0
90
0.005
0.007
0.01
0.02
102
102
-100
60
45
20
±10
Max
Units
W
W
W
W
W
W
W
W
%
Ω
Ω
A
°C
°C
A
V
RMS
%
%
%
%
%
dB
dB
dB
dB
dB
kΩ
mV
Test Conditions/Comments
R
L
= 6Ω, PV
DD
= 20 V, 1 kHz (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
@ <0.01% THD+N
@ 10% THD+N (FTC)
f
IN
=1 kHz, P
O
= 5 W, R
L
= 6Ω
@1A
@1A
Die temperature
Die temperature
PGA gain = 0 dB
PGA = 0 dB, P
O
= 5 W
PGA = 6 dB, P
O
= 5 W
PGA = 12 dB, P
O
= 5 W
PGA = 18 dB, P
O
= 5 W
-60 dB Input
Measured channel input = 0 V
RMS
,
other channel = 1 kHz at 5W
20 Hz - 1 kHz
20 Hz – 20 kHz
AINL and AINR analog inputs
Signal/Noise Ratio (SNR)
Dynamic Range (DNR)
Crosstalk
Power supply rejection (PSRR)
DC SPECIFICATIONS
Input Impedance
Output DC Offset Voltage
Rev. PrA – 1/20/05 | Page 3 of 16
AD199x
Preliminary Technical Data
Parameter
POWER SUPPLIES
Supply Voltage AV
DD
Supply Voltage DV
DD
Supply Voltage PV
DDX
Powerdown Current
AV
DD
DV
DD
PV
DDX
Mute Current
AV
DD
DV
DD
PVDD
Quiesent Current
AV
DD
DV
DD
PV
DDX
Operating Current
AV
DD
DV
DD
PV
DD
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current on Digital Inputs
Min
4.5
4.5
6.5
Typ
5
5
8-20
0.1
0.1
19
19
2.7
1.5
20
5.2
3.2
22
5.8
Max
5.5
5.5
22.5
0.5
0.5
25
Units
V
V
V
Test Conditions/Comments
RST/PDN held low
µA
µA
µA
MUTE held low
mA
mA
mA
Inputs Grounded, Non-Overlap Time = TBD
mA
mA
mA
V
IN
= 1V
RMS
, P
O
= 5 W
mA
mA
A
V
V
V
V
µA
4
2.0
DV
DD
-0.8
0.4
10
DV
DD
0.8
per FET
@ 2 mA
@ 2 mA
Rev. PrA – 1/20/05 | Page 4 of 16
Preliminary Technical Data
AD199x
Table 2 DIGITAL TIMING (Guaranteed over -40°C to +85°C, AV
DD
= DV
DD
= 5.0V ± 10%, PV
DDX
=12V ± 10%, Non Overlap Time
t
NOL
= Shortest, See Table 6: Non-Overlap Time Settings)
Parameter
t
PDRP
t
MPDL
t
MUTEDLY
Min
500
Typ
Max
5
1
Units
ns
µs
sec
Comments
RST/PDN minimum low pulsewidth
MUTE asserted to output initial response
RST/PDN high to MUTE high delay
OUTL+/
O UTR+
OUTL-/
OUTR-
t
NOL
t
NOL
Figure 2. Output Timing
MUTE
t PST
t PST
OUTX
tMPDL
t MPDL
Figure 3. Mute Timing
RESET
MUTE
t
MUTEDLY
Figure 4. Reset to Mute Delay
Rev. PrA – 1/20/05 | Page 5 of 16
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