Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
Specified for V
DD
of 2.7 V to 5.25 V
Low power:
0.9 mW max at 100 kSPS with V
DD
= 3 V
3 mW max at 100 kSPS with V
DD
= 5 V
Pseudo differential analog input
Wide input bandwidth:
70-dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®/QSPI™/
MICROWIRE™/DSP compatible
Automatic power-down mode
8-lead SOT-23 package
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN+
T/H
V
IN–
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
REF
SCLK
AD7457
SDATA
CONTROL LOGIC
CS
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GND
03157-0-013
Figure 1.
GENERAL DESCRIPTION
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies in excess of 1 MHz. The reference voltage for the
AD7457 is applied externally to the V
REF
pin and can range from
100 mV to V
DD
, depending on what suits the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1.
2.
Operation with 2.7 V to 5.25 V power supplies.
Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
Pseudo differential analog input.
Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power
consumption to be reduced.
Variable voltage reference input.
No pipeline delay.
Accurate control of the sampling instance via the CS input
and once-off conversion control.
ENOB > 10 bits typically with 500 mV reference.
3.
4.
5.
6.
7.
8.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
AD7457
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Functional Descriptions.......................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Circuit Information.................................................................... 11
Converter Operation.................................................................. 11
ADC Transfer Function............................................................. 11
Typical Connection Diagram ................................................... 11
Analog Input ............................................................................... 12
Analog Input Structure.............................................................. 12
Digital Inputs .............................................................................. 13
Reference Section ....................................................................... 13
Serial Interface ............................................................................ 13
Power Consumption .................................................................. 14
Microprocessor Interfacing....................................................... 14
Application Hints ........................................................................... 16
Grounding and Layout .............................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD7457
SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 100 kSPS, V
REF
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR)
2
Signal to (Noise + Distortion) (SINAD)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
2
Intermodulation DIstortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
2
Aperture Jitter
2
Full-Power Bandwidth
2,3
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
2
Differential Nonlinearity (DNL)
2
Offset Error
2
Gain Error
2
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
V
IN+
V
IN– 4
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage
DC Leakage Current
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN6
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
6
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
2
Throughput Rate
Test Conditions/Comments
f
IN
= 30 kHz
B Version
1
71
70
−75
−75
−80
−80
5
50
20
2.5
12
±1
±0.95
±4.5
±2
V
REF
V
REF
−0.1 to +0.4
−0.1 to +1.5
±1
30/10
2.5
5
±1
10/30
2.4
0.8
±1
10
2.8
2.4
0.4
±1
10
Straight
natural binary
16
1
100
Unit
dB min
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
V
V
V
µA max
pF typ
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
−84 dB typ
−86 dB typ
fa = 25 kHz; fb = 35 kHz
@ −3 dB
@ −0.1 dB
Guaranteed no missed codes to 12 bits
V
IN+
− V
IN–
V
DD
= 2.7 V to 3.6 V
V
DD
= 4.75 V to 5.25 V
When in track/hold
±1% tolerance for specified performance
When in track/hold
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, I
SOURCE
= 200 µA
V
DD
= 2.7 V to 3.6 V, I
SOURCE
= 200 µA
I
SINK
= 200 µA
1.6 µs with a 10 MHz SCLK
See Serial Interface section
SCLK cycles
µs max
kSPS max
Rev. 0 | Page 3 of 20
AD7457
Parameter
POWER REQUIREMENTS
V
DD
I
DD7,8
During Conversion
6
Normal Mode (Static)
Normal Mode (Operational)
Power-Down
Power Dissipation
Normal Mode (Operational)
Power-Down
Test Conditions/Comments
B Version
1
Unit
2.7/5.25
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
SCLK on or off
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
SCLK on or off
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V; SCLK on or off
V
DD
= 3 V; SCLK on or off
1.5
1.2
0.5
0.7
0.33
1
3
0.9
5
3
V min/max
mA max
mA max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
1
2
Temperature ranges as follows: B version: −40°C to +85°C.
See Terminology section.
3
Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4
A dc input is applied to V
IN–
to provide a pseudo ground for V
IN+.
5
The AD7457 is functional with a reference input in the range 100 mV to V
DD
.
6
Guaranteed by characterization.
7
See Power Consumption section.
8
Measured with a full-scale dc input.
Rev. 0 | Page 4 of 20
AD7457
TIMING SPECIFICATIONS
1
V
DD
= 2.7 V to 5.25 V, f
SCLK
= 10 MHz, f
S
= 100 kSPS, V
REF
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
f
SCLK2
t
CONVERT
t
2
t
33
t
43
t
5
t
6
t
7
t
84
t
POWER-UP5
t
POWER-DOWN
1
Limit at T
MIN
, T
MAX
10
10
16 × t
SCLK
1.6
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
7.4
Unit
kHz min
MHz max
µs max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
µs min
Description
t
SCLK
= 1/f
SCLK
CS rising edge to SCLK falling edge setup time
Delay from CS rising edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
Minimum time spent in power-down
The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. See Figure 2 and the Serial Interface section.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V, and the time required for the output to
cross 0.4 V or 2.0 V for V
DD
= 3 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
5
See Power Consumption section.
POWER
UP
CONVERT
START
HOLD
TRACK
T
POWERUP
T
ACQUISTION
AUTOMATIC
POWER DOWN
TRACK
T
POWERUP
CS
T
ACQUISITION
SCLK
t
2
t
5
t
6
0
DB11 DB10
SDATA
THREE-STATE
0
0
0
DB2
DB1
DB0
THREE-STATE
4 LEADING ZEROS
Figure 2. AD7457 Serial Interface Timing Diagram
Rev. 0 | Page 5 of 20
03157-0-001
t
3
t
4
t
7
t
8
T
POWERDOWN
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