IS24C02D
IS24C02D
2-WIRE (I C)
2
2K-bit
SERIAL EEPROM
Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical
equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for
the best performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for
products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
1
IS24C02D
TAbLE Of COnTEnTS
features ……………………………………………………….…………….................3
Description ………………………………………………...……………….................3
functional block Diagram ……………………………………………….................4
Pin Configuration & Description ………………………………………..................5
Device Operations …..…………………………………………………….................5
Absolute Maximum Ratings ……………………………………………..................13
Operating Range …………………………………………………………..................13
DC Characteristics ………………………………………………………...................14
AC Characteristics ………………………………………………………...................14
Ordering Information ……………………………………………………...................16
Packaging Information ….………………………………………………...................17
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
IS24C02D
2K-bit 2-WIRE SERIAL CMOS EEPROM
AUGUST 2009
fEATURES
• Two-Wire Serial Interface, I
2
C
TM
compatible
– Bidirectional data transfer protocol
• Wide Voltage Operation
– Vcc = 1.8V to 5.5V
• Speed
– 400 kHz (2.5V) and 1 MHz (5.0V)
• Memory: 256 x 8-bit (2Kb)
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
• Page Write Mode (up to 16 bytes)
• Low Power
– Operating Current: 2 mA or higher (5V)
– Standby Current: 1 µA or less (1.8V)
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle with auto clear
– 5 ms max. @ 2.5V
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Industrial grade
• Packages (8-pin): SOIC/SOP, TSSOP, PDIP,
MSOP, DFN.
DESCRIPTIOn
The IS24C02D is an electrically erasable programmable
read only memory device that utilizes the standard
serial 2-wire interface for communications. This
EEPROM operates in a wide voltage range of 1.8V to
5.5V to be compatible with most application voltages.
The IS24C02D has an embedded memory array of
2,048-bits (256 x 8), and is organized in 16 pages of 16
bytes each. So page-write mode is capable of up to 16
bytes. In addition, software write-protection feature is
initiated with a unique irreversible instruction. After this
command is transmitted, the first 128 bytes of the array
become permanently read-only. This feature is designed
for specific applications such as, DIMMs. ISSI designed
the IS24C02D as a low-cost and low-power 2-wire
EEPROM solution. The device is offered in lead-free,
RoHS, halogen free or Green. The available package
types are 8-pin SOIC, TSSOP, PDIP, MSOP, and DFN.
The IS24C02D maintains compatibility with the popular
2-wire bus protocol, so it is easy to use in applications
implementing this bus type. The simple bus consists
of the Serial Clock wire (SCL) and the Serial Data
wire (SDA). Using the bus, a Master device such as
a microcontroller is usually connected to one or more
Slave devices such as the IS24C02D. The bit stream
over the SDA line includes a series of bytes, which
identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data,
if appropriate. The IS24C02D has a Write Protect
pin (WP) to allow blocking of any write instruction
transmitted over the bus.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
3
IS24C02D
FUNCTIONAL BLOCK DIAGRAM
Vcc
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
SDA
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
A1
A2
WORD ADDRESS
COUNTER
X
DECODER
SCL
CONTROL
LOGIC
00H-7FH
ARRAY
80H-FFH
Y
DECODER
GND
nMOS
ACK
Clock
DI/O
>
DATA
REGISTER
For applications related inquiries, please refer to the EEPROM Application Support section of our website.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
IS24C02D
PIN CONFIGURATION
8-Pin DIP, SOIC, TSSOP, MSOP
8-pad Dfn
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIn DESCRIPTIOnS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read
-only regardless of the setting of the WP pin.
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
DEVICE OPERATIOn
The IS24C02D features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I
2
C
TM
.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an
open drain output and can be wire Or'ed with other open
drain or open collector outputs. The SDA bus requires a
pullup resistor to Vcc.
2-WIRE bUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C02D is the Slave device on the bus.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that
are hardwired or left unconnected for hardware flexibility.
When pins are hardwired, as many as eight devices may
be addressed on a single bus system. When the pins are
not hardwired, the default values of A0, A1, and A2 are
zero.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
07/30/09
5
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