C8051F350/1/2/3
8 k ISP Flash MCU Family
Analog Peripherals
-
24 or 16-Bit ADC
•
•
•
•
•
•
No missing codes
0.0015% nonlinearity
Programmable conversion rates up to 1 ksps
8-Input multiplexer
1x to 128x PGA
Built-in temperature sensor
High Speed 8051 µC Core
-
Pipelined Instruction architecture; executes 70% of
-
-
Memory
-
768 Bytes (256 + 512) On-Chip RAM
-
8 kB Flash; In-system programmable in 512-byte
Sectors
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput
Expanded interrupt handler
-
-
Two 8-Bit Current Output DACs
Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (0.4 µA)
On-chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
-
intrusive in-system debug (No emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-Chips, target pods, and sockets
Low Cost,
Complete
Development Kit
Digital Peripherals
-
17 Port I/O; All 5 V tolerant with high sink current
-
Enhanced UART, SMBus™, and SPI™ Serial Ports
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Four general purpose 16-bit counter/timers
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16-bit programmable counter array (PCA) with three
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capture/compare modules
Real time clock mode using PCA or timer and exter-
nal clock source
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Supply Voltage 2.7 to 3.6 V
-
Typical operating current:
5.8 mA @ 25 MHz;
-
Typical stop mode current:
Temperature Range: –40 to +85 °C
11 µA @ 32 kHz
0.1 µA
Clock Sources
-
Internal Oscillator: 24.5 MHz with ± 2% accuracy
-
supports UART operation
External Oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
Clock multiplier to achieve 50 MHz internal clock
Can switch between clock sources on-the-fly
-
-
28-Pin QFN or 32-Pin LQFP Package
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5 x 5 mm PCB footprint with 28-QFN
CROSSBAR
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Port 0
24/16-bit
ADC
+
-
8-bit
IDAC
8-bit
IDAC
Port 1
P2.0
TEMP
SENSOR
VOLTAGE
COMPARATOR
24.5 MHz PRECISION INTERNAL OSCILLATOR
WITH CLOCK MULTIPLIER
HIGH-SPEED CONTROLLER CORE
8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR
WDT
Rev. 1.1 5/07
Copyright © 2007 by Silicon Laboratories
C8051F35x
C8051F350/1/2/3
N
OTES
:
2
Rev. 1.1
C8051F350/1/2/3
Table of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller................................................................................... 21
1.1.1. Fully 8051 Compatible Instruction Set...................................................... 21
1.1.2. Improved Throughput ............................................................................... 21
1.1.3. Additional Features .................................................................................. 21
1.2. On-Chip Debug Circuitry................................................................................... 22
1.3. On-Chip Memory............................................................................................... 23
1.4. 24 or 16-Bit Analog to Digital Converter (ADC0) .............................................. 24
1.5. Two 8-bit Current-Mode DACs.......................................................................... 25
1.6. Programmable Comparator .............................................................................. 26
1.7. Serial Ports ....................................................................................................... 26
1.8. Port Input/Output............................................................................................... 27
1.9. Programmable Counter Array ........................................................................... 28
2. Absolute Maximum Ratings .................................................................................. 29
3. Global DC Electrical Characteristics .................................................................... 30
4. Pinout and Package Definitions............................................................................ 31
5. 24 or 16-Bit Analog to Digital Converter (ADC0) ................................................. 41
5.1. Configuration..................................................................................................... 42
5.1.1. Voltage Reference Selection.................................................................... 42
5.1.2. Analog Inputs ........................................................................................... 42
5.1.3. Modulator Clock ....................................................................................... 43
5.1.4. Decimation Ratio ...................................................................................... 43
5.2. Calibrating the ADC .......................................................................................... 44
5.2.1. Internal Calibration ................................................................................... 44
5.2.2. System Calibration ................................................................................... 44
5.2.3. Calibration Coefficient Storage................................................................. 44
5.3. Performing Conversions ................................................................................... 46
5.3.1. Single Conversions .................................................................................. 46
5.3.2. Continuous Conversions .......................................................................... 46
5.3.3. ADC Output .............................................................................................. 46
5.3.4. Error Conditions ....................................................................................... 47
5.4. Offset DAC........................................................................................................ 47
5.5. Burnout Current Sources .................................................................................. 47
5.6. Analog Multiplexer ............................................................................................ 59
6. 8-Bit Current Mode DACS (IDA0 and IDA1).......................................................... 67
6.1. IDAC Output Scheduling................................................................................... 68
6.1.1. Update Output On-Demand ..................................................................... 68
6.1.2. Update Output Based on Timer Overflow ................................................ 68
6.1.3. Update Output Based on CNVSTR Edge................................................. 68
6.2. IDAC Output Mapping....................................................................................... 68
6.3. IDAC External Pin Connections ........................................................................ 71
7. Voltage Reference .................................................................................................. 73
8. Temperature Sensor............................................................................................... 77
Rev. 1.1
3
C8051F350/1/2/3
9. Comparator0 ........................................................................................................... 79
9.1. Comparator0 Inputs and Outputs...................................................................... 83
10. CIP-51 Microcontroller ........................................................................................... 87
10.1.Instruction Set................................................................................................... 89
10.1.1.Instruction and CPU Timing ..................................................................... 89
10.1.2.MOVX Instruction and Program Memory ................................................. 89
10.2.Register Descriptions ....................................................................................... 93
10.3.Power Management Modes.............................................................................. 96
10.3.1.Idle Mode ................................................................................................. 96
10.3.2.Stop Mode................................................................................................ 96
11. Memory Organization and SFRs ........................................................................... 99
11.1.Program Memory.............................................................................................. 99
11.2.Data Memory .................................................................................................. 100
11.3.General Purpose Registers ............................................................................ 100
11.4.Bit Addressable Locations .............................................................................. 100
11.5.Stack............................................................................................................... 100
11.6.Special Function Registers............................................................................. 101
12. Interrupt Handler .................................................................................................. 105
12.1.MCU Interrupt Sources and Vectors............................................................... 105
12.2.Interrupt Priorities ........................................................................................... 105
12.3.Interrupt Latency............................................................................................. 105
12.4.Interrupt Register Descriptions ....................................................................... 107
12.5.External Interrupts .......................................................................................... 111
13. Prefetch Engine .................................................................................................... 113
14. Reset Sources....................................................................................................... 115
14.1.Power-On Reset ............................................................................................. 116
14.2.Power-Fail Reset / VDD Monitor .................................................................... 117
14.3.External Reset ................................................................................................ 118
14.4.Missing Clock Detector Reset ........................................................................ 118
14.5.Comparator0 Reset ........................................................................................ 118
14.6.PCA Watchdog Timer Reset .......................................................................... 118
14.7.Flash Error Reset ........................................................................................... 118
14.8.Software Reset ............................................................................................... 118
15. Flash Memory ....................................................................................................... 121
15.1.Programming The Flash Memory ................................................................... 121
15.1.1.Flash Lock and Key Functions ............................................................... 121
15.1.2.Flash Erase Procedure .......................................................................... 121
15.1.3.Flash Write Procedure ........................................................................... 122
15.2.Non-volatile Data Storage .............................................................................. 123
15.3.Security Options ............................................................................................. 123
16. External RAM ........................................................................................................ 127
17. Oscillators ............................................................................................................. 129
17.1.Programmable Internal Oscillator ................................................................... 129
17.2.External Oscillator Drive Circuit...................................................................... 131
17.2.1.Clocking Timers Directly Through the External Oscillator...................... 131
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C8051F350/1/2/3
17.2.2.External Crystal Example....................................................................... 131
17.2.3.External RC Example............................................................................. 133
17.2.4.External Capacitor Example................................................................... 133
17.3.Clock Multiplier ............................................................................................... 135
17.4.System Clock Selection.................................................................................. 136
18. Port Input/Output.................................................................................................. 137
18.1.Priority Crossbar Decoder .............................................................................. 139
18.2.Port I/O Initialization ....................................................................................... 141
18.3.General Purpose Port I/O ............................................................................... 144
19. SMBus ................................................................................................................... 151
19.1.Supporting Documents ................................................................................... 152
19.2.SMBus Configuration...................................................................................... 152
19.3.SMBus Operation ........................................................................................... 152
19.3.1.Arbitration............................................................................................... 153
19.3.2.Clock Low Extension.............................................................................. 154
19.3.3.SCL Low Timeout................................................................................... 154
19.3.4.SCL High (SMBus Free) Timeout .......................................................... 154
19.4.Using the SMBus............................................................................................ 155
19.4.1.SMBus Configuration Register............................................................... 156
19.4.2.SMB0CN Control Register ..................................................................... 159
19.4.3.Data Register ......................................................................................... 162
19.5.SMBus Transfer Modes.................................................................................. 163
19.5.1.Master Transmitter Mode ....................................................................... 163
19.5.2.Master Receiver Mode ........................................................................... 164
19.5.3.Slave Receiver Mode ............................................................................. 165
19.5.4.Slave Transmitter Mode ......................................................................... 166
19.6.SMBus Status Decoding................................................................................. 167
20. UART0.................................................................................................................... 171
20.1.Enhanced Baud Rate Generation................................................................... 172
20.2.Operational Modes ......................................................................................... 173
20.2.1.8-Bit UART ............................................................................................. 173
20.2.2.9-Bit UART ............................................................................................. 174
20.3.Multiprocessor Communications .................................................................... 174
21. Serial Peripheral Interface (SPI0) ........................................................................ 181
21.1.Signal Descriptions......................................................................................... 182
21.1.1.Master Out, Slave In (MOSI).................................................................. 182
21.1.2.Master In, Slave Out (MISO).................................................................. 182
21.1.3.Serial Clock (SCK) ................................................................................. 182
21.1.4.Slave Select (NSS) ................................................................................ 182
21.2.SPI0 Master Mode Operation ......................................................................... 183
21.3.SPI0 Slave Mode Operation ........................................................................... 185
21.4.SPI0 Interrupt Sources ................................................................................... 185
21.5.Serial Clock Timing......................................................................................... 186
21.6.SPI Special Function Registers ...................................................................... 186
Rev. 1.1
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