21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16244
3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
Product Features
· Advanced low power CMOS design for 2.7V to 3.6V V
CC
operation
· Supports 5V input/output tolerance in mixed signal mode
operation
· Function compatible with LVT family of products
· Balanced ±24mA output drive
· Typical V
OLP
(Output Ground Bounce)
<0.8V at V
CC
=3.3V, T
A
=25°C
· I
off
and Power Up/Down 3-State support live insertion
· Latch-up performance exceeds 200mA Per JESD78
· ESD protection exceeds JESD 22
- 2000V Human-Body Model (A114-B)
- 200V Machine Model (A115-A)
· Available Packages (Pb-free available):
- 48-pin 240-mil wide plastic TSSOP (A48)
- 48-pin 300-mil wide plastic SSOP (V48)
· Industrial Temperature: -40°C to +85°C
Product Description
Pericom Semiconductor’s PI74LVTC series of logic circuits are
produced using the Company’s advanced CMOS technology,
achieving industry leading speed.
The PI74LVTC16244 is a non-inverting 16-bit buffer and line
driver designed for low-voltage 2.7V to 3.6V V
CC
operation, with
the capability of interfacing to the 5V system environment. This
buffer/driver is designed specifically to improve both the perfor-
mance and density of 3-State memory address drivers, clock
drivers, and bus-oriented receivers and transmitters. The device
can be used as four 4-bit buffers, two 8-bit buffers, or one
16-bit buffer.
When V
CC
is between 0 to 1.5V during power up or power down,
the device is in the high-impedance state. To ensure the high-
impedance state above 1.5V, OE should be tied to Vcc through a
pullup resistor; the minimum value of the resistor is determined by
the current sinking capability of the driver.
The device fully supports live-insertion with its I
off
and power-up/
down 3-state. The I
off
circuitry disables the outputs when the
power is off, preventing the backflow of damaging current through
the device. Power-up/down 3-state places the outputs in the high-
impedance state during power up or power down, preventing driver
conflict.
Logic Block Diagram
1OE
1A1
1
47
2
3OE
1Y1
3A1
25
36
13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE
2A1
48
41
8 2Y1
9
4OE
4A1
24
30
19
4Y1
2A2
40
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
1
PS8652A
05/19/03
Truth Table
xOE
L
L
H
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16244
3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply voltage range, V
CC
............................ –0.5V to +6.5V
Input voltage range, V
I
(1)
............................... –0.5V to +6.5V
Voltage range applied to any output in the
high-impedance or power-off state, V
O
(1)
..... –0.5V to +6.5V
Voltage range applied to any output in the
active state, V
O
(1), (2)
............................... –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ................................... –50mA
Output clamp current, I
OK
(V
O
<0) .............................. –50mA
Continous Output Current I
O
........................................ ±50mA
Continous Current through each VCC or GND pin ............ ±100mA
Package thermal impedance,
θ
JA
(3)
: package A ....... 104°C/W
package V ... 94°C/W
Storage Temperature range, T
stg
.................... –65°C to 150°C
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
1. Input negative-voltage and output voltage ratings may be exceeded if the
input and output clamp current ratings are observed.
2. This value is limited to 6.5V maximum.
3. The package thermal impedance is calculated in accordance with JESD
51.
Product Pin Description
Pin Name
xOE
xAx
xYx
GND
V
C C
Inputs
3- State Outputs
Ground
Power
De s cription
3- State Output Enable Inputs (Active LOW)
Product Pin Configuration
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
(4)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
48-Pin
A, V
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3Y2
Inputs
xAx
H
L
X
Outputs
xYx
H
L
Z
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
Notes:
4. H = High Signal Level
L = Low Signal Level
X = Don’t Care or Irrelevant
Z = High Impedance
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16244
3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
Recommended Operating Conditions
(5)
M in.
V
C C
V
IH
V
IL
V
I
V
O
Supply Voltage
High- level Input Voltage
Low- level Input Voltage
Input Voltage
Output Voltage
High or Low State
3- State
V
C C
= 2.7V
V
C C
= 3.0V to 3.6V
V
C C
= 2.7V
V
C C
= 3.0V to 3.6V
Operating
V
C C
= 2.7V to 3.6V
V
C C
= 2.7V to 3.6V
0
0
0
2.7
2.0
0.8
5.5
V
C C
5.5
–12
– 24
12
24
10
150
– 40
+85
ns/V
µ
s/V
°C
mA
V
M a x.
3.6
Units
I
O H
High- level output current
I
O
L Low- level output current
∆
t/
∆
v Input transition rise or fall rate
∆
t/
∆V
C C
Power- up ramp rate
T
A
Operating free- air temperature
Notes:
5. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
PS8652A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16244
3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C)
Parame te rs
V
IK
De s cription
Clamp Diode Voltage
V
C C
= 2.7V
V
C C
= 2.7V to 3.6V
V
O H
Out
p
ut High Voltage
V
C C
= 2.7V
V
C C
= 3V
V
C C
= 2.7V to 3.6V
V
O L
Out
p
ut Low Voltage
V
C C
= 2.7V
V
C C
= 3V
I
I
I
O FF
I
O Z
I
O ZPU
I
O ZPD
I
C C
∆I
C C
Input
L
eakage Current
Power Off
Output Leakage
Current
Te s t Conditions
I
I
= –18mA
I
O H
= –100µA
I
O H
= –12mA
I
O H
= –12mA
I
O H
= –24mA
I
O L
= 100µA
I
O L
= 12mA
I
O L
= 12mA
I
O L
= 24mA
V
I
= 0
V
to 5.5V
V
I
or V
O
= 0
V
to 5.5V
V
O
=
0
V to 5.5V,
V
O
= 0.5V to 5.5V,
OE = don't care
V
O
= 0.5V to 5.5V,
OE = don't care
V
I
= V
C C
or GND
3.6V
≤
V
I
≤
5.5V
One input at V
C C
- 0.6V
(
6
)
Other inputs at V
C C
or GND
I
O
= 0
M in.
V
C C
–0.2V
2.2
2.4
2.2
M a x.
–1.2V
Units
V
0 .2
0.4
0.4
0.55
±5
±5
±5
±5
±5
100
10 0
V
C C
= 0V to 3.6V
V
C C
= 0V
V
C C
= 2.7V to 3.6V
V
C C
= 0
V
to 1.5V
V
C C
= 1.5V to 0V
V
C C
= 2.7V to 3.6V
V
C C
=
2.7
V to 3.6V
3- State Output Leakage
Current
Power- Up 3- State Current
Power- Down 3- State
Current
Quiescent Power Supply
Current
Increase in I
C C
µA
Notes:
6. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
4
PS8652A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16244
3.3V 16-Bit Buffer/Line Driver
with 3-State Outputs
Capacitance
Parame te rs
C
I
C
O
C
PD
De s cription
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(8)
Te s t Conditions
V
CC
= 3.3V, V
I
= V
CC
or GND
V
CC
= 3.3V, V
O
= V
CC
or GND
V
CC
= 3.3V, V
I
= 0V or V
CC,
f =10 MHz
Typ.
(7)
3.7
7
15
pF
Units
Notes:
7. All typical values are measured at VCC = 3.3V, TA = 25°C.
8. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current
sumption (I
CCD
) at no output loading and operating at 50% duty cycle, C
PD
is related to I
CCD
dynamic operating
expression: I
CCD
= (C
PD
)(V
CC
)(f
IN
)+(I
CC
static)
con-
current by the
Switching Characteristics Over Operating Range
V
CC
= 3.3V ±0.3V
Parame te rs
D e s cription
From
(Input)
To
(Outpu-
t)
C
L
= 50pF, R
L
= 500Ohm
M in.
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(O)
Propagation Delay
A
Y
1.0
1.0
1.0
1.0
1. 0
1.0
Typ.
(9)
2.5
2.5
2.9
3.0
2.5
2.4
M a x.
3.4
3.4
4.2
4.2
4.0
3.9
0.5
V
CC
= 2.7V
C
L
= 50pF, R
L
=
500Ohm
M in.
M a x.
3.8
3.8
5.0
5.0
4.7
4.3
ns
Units
O utput Enable Time
OE
Y
O utput Disable Time
O utput to O utput
Skew
(10)
OE
Y
Notes:
9. All typical values are measured at VCC = 3.3V, TA = 25°C.
10. Skew between any two outputs, switching in the same direction.
5
PS8652A
05/19/03
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