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Semiconductor Products Sector
Order Number: MPC603E7TEC/D
Rev. 4, 5/2000
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Technical Data
PowerPC
ª
603e RISC Microprocessor Family:
PID7t-603e Hardware SpeciÞcations
The PowerPC 603eª microprocessor is an implementation of the PowerPC family of reduced instruction
set computing (RISC) microprocessors. In this document, the term Ô603eÕ is used as an abbreviation for the
PowerPC 603e microprocessor. The PowerPC 603e microprocessors are available from Motorola as
MPC603e.
The 603e is implemented in several semiconductor fabrication processes. Different processes may require
different supply voltages and may have other electrical differences but will have the same functionality. As
a technical designator to distinguish between 603e implementations in various processes, a preÞx composed
of the processor version register (PVR) value and a process identiÞer (PID) is assigned to the various
implementations as shown below:
Table 1PowerPC 603e Microprocessors from Motorola
Technical
Designator
PID6-603e
PID7v-603e
PID7t-603e
Process
0.5 µm CMOS, 4LM
0.35 µm CMOS, 5LM
0.29 µm CMOS, 5LM
Core
Voltage
3.3 V
2.5 V
2.5 V
I/O
Voltage
3.3 V
3.3 V
3.3 V
5-Volt
Tolerant
Yes
Yes
Yes
Part Number
MPC603E
XPC603P (end-of-life)
MPC603R
This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc., 2000. All rights reserved.
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Overview
This document describes the pertinent physical characteristics of the PID7t-603e from Motorola. For
functional characteristics of the 603e, refer to the
PowerPC 603e RISC Microprocessor UserÕs Manual
.
This document contains the following topics:
Topic
Page
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Section 1.1, ÒOverviewÓ
Section 1.2, ÒFeaturesÓ
Section 1.3, ÒGeneral ParametersÓ
Section 1.4, ÒElectrical and Thermal CharacteristicsÓ
Section 1.5, ÒPin AssignmentsÓ
Section 1.6, ÒPinout ListingsÓ
Section 1.7, ÒPackage DescriptionsÓ
Section 1.8, ÒSystem Design InformationÓ
Section 1.9, ÒOrdering InformationÓ
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
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1.1 Overview
This section describes the features of the 603e and describes brießy how those units interact.
The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set
computing (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture
speciÞcation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and
ßoating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture
provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit
architecture.
The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and
sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the 603e to
automatically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock.
Instructions can execute out of order for increased performance; however, the 603e makes completion
appear sequential.
The 603e integrates Þve execution unitsÑan integer unit (IU), a ßoating-point unit (FPU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute Þve
instructions in parallel and the use of simple instructions with rapid execution times yield high efÞciency
and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is
pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches
for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs
contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and
ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also
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Features
supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603e provides a
three-state coherency protocol that supports the exclusive, modiÞed, and invalid cache states. This protocol
is a compatible subset of the MESI (modiÞed/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers
for memory accesses, and supports memory-mapped I/O.
The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility
with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The CBGA package
supports speed bins of 200 MHz, 266 MHz, and 300 MHz. The PBGA package is a pin-compatible drop in
replacement for the CBGA; however this package only supports speeds up to 200 MHz.
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1.2 Features
This section summarizes features of the 603eÕs implementation of the PowerPC architecture. Major features
of the 603e are as follows:
¥
High-performance, superscalar microprocessor
Ñ As many as three instructions issued and retired per clock
Ñ As many as Þve instructions in execution per clock
Ñ Single-cycle execution for most instructions
Ñ Pipelined FPU for all single-precision and most double-precision operations
¥
Five independent execution units and two register Þles
Ñ BPU featuring static branch prediction
Ñ A 32-bit IU
Ñ Fully IEEE 754-compliant FPU for both single- and double-precision operations
Ñ LSU for data transfer between data cache and GPRs and FPRs
Ñ SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
integer add/compare instructions
Ñ Thirty-two GPRs for integer operands
Ñ Thirty-two FPRs for single- or double-precision operands
¥
High instruction and data throughput
Ñ Zero-cycle branch capability (branch folding)
Ñ Programmable static branch prediction on unresolved conditional branches
Ñ Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
Ñ A six-entry instruction queue that provides lookahead capability
Ñ Independent pipelines with feed-forwarding that reduces data dependencies in hardware
Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU replacement
algorithm
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General Parameters
Ñ 16-Kbyte instruction cacheÑfour-way set-associative, physically addressed; LRU replacement
algorithm
Ñ Cache write-back or write-through operation programmable on a per page or per block basis
Ñ BPU that performs CR lookahead operations
Ñ Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
segment size
Ñ A 64-entry, two-way set-associative ITLB
Ñ A 64-entry, two-way set-associative DTLB
Ñ Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
Ñ Software table search operations and updates supported through fast trap mechanism
Ñ 52-bit virtual address; 32-bit physical address
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¥
Facilities for enhanced system performance
Ñ A 32- or 64-bit split-transaction external data bus with burst transfers
Ñ Support for one-level address pipelining and out-of-order bus transactions
¥
Integrated power management
Ñ Low-power 2.5/3.3-volt design
Ñ Internal processor/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,
5.5:1, and 6:1 ratios
Ñ Three power saving modes: doze, nap, and sleep
Ñ Automatic dynamic power reduction when internal functional units are idle
¥
In-system testability and debugging features through JTAG boundary-scan capability
1.3 General Parameters
The following list provides a summary of the general parameters of the PID7t-603e:
Technology
Die size
Transistor count
Logic design
Package
Core power supply
I/O power supply
0.29
µ
m CMOS, Þve-layer metal
5.65 mm x 7.7 mm (44 mm
2
)
2.6 million
Fully-static
255 ceramic ball grid array (CBGA)
or 225 thin map plastic ball grid array (PBGA)
2.5 ± 5% V dc
3.3 ± 5% V dc
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Electrical and Thermal Characteristics
1.4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical speciÞcations and thermal characteristics for the
PID7t-603e.
1.4.1 DC Electrical Characteristics
The tables in this section describe the PID7t-603e DC electrical characteristics. Table 2 provides the
absolute maximum ratings.
Table 2. Absolute Maximum Ratings
Characteristic
Core supply voltage
Vdd
AVdd
OVdd
V
in
T
stg
Symbol
Value
–0.3 to 2.75
–0.3 to 2.75
–0.3 to 3.6
–0.3 to 5.5
–55 to 150
Unit
V
V
V
V
°C
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PLL supply voltage
I/O supply voltage
Input voltage
Storage temperature range
Notes
:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect
device reliability or cause permanent damage to the device.
2.
Caution
: V
in
must not exceed OVdd by more than 2.5 V at any time, including during power-on reset.
3.
Caution
: OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time, including during power-on reset.
4.
Caution
: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time, including during power-on reset.
Table 3 provides the recommended operating conditions for the PID7t-603e.
Table 3. Recommended Operating Conditions
Characteristic
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Die-junction temperature
Vdd
AVdd
OVdd
V
in
Tj
Symbol
Value
2.375 to 2.625
2.375 to 2.625
3.135 to 3.465
GND to 5.5
0 to 105
Unit
V
V
V
V
°C
Note:
These are the recommended and tested operating conditions. Proper device operation outside of
these conditions is not guaranteed.
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