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1
DS1014_02.0
Digital Monitoring
Other Board Circuitry
ispPAC-POWR1014/A Data Sheet
MOSFET drivers. In high-voltage mode these outputs can provide up to 12V for driving the gates of n-channel
MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable
ramp rate for both ramp up and ramp down.
The ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer
®
software. Control sequences are written to
monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
MON
voltage through the I
2
C bus or JTAG interface of the
ispPAC-POWR1014A device.
The I
2
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
MON
inputs, read back the status of each of the V
MON
comparator and PLD outputs, control logic signals IN2 to IN4 and
control the output pins (ispPAC-POWR1014A only). The JTAG interface can be used to read out all I
2
C registers
during manufacturing.
Figure 1. ispPAC-POWR1014/A Block Diagram
ADC*
MEASUREMENT
CONTROL LOGIC*
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
10 ANALOG INPUTS
AND
V
OLTAGE MONITORS
4 DIGITAL
INPUTS
2 FET
DRI
V
ERS
HVOUT1
HVOUT2
OUTPUT ROUTING
POOL
CPLD
24 MACROCELLS
53 INPUTS
IN1
IN2
IN3
IN4
JTAG LOGIC
CLOCK
OSCILLATOR
TIMERS
(4)
I
2
C
INTERFACE
OUT3/(SMBA*)
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
12 OPEN-DRAIN
DIGITAL OUTPUTS
GNDA
SCL*
SDA*
*ispPAC-POWR1014A only.
VCCINP
ATDI
TDI
TDISEL
TCK
TMS
TDO
V
CCJ
PLDCLK
MCLK
RESET
b
VCCD
(2)
VCCA
GNDD (2)
APS
2
ispPAC-POWR1014/A Data Sheet
Pin Descriptions
Number
44
46
47
48
25
26
27
28
32
33
34
35
36
37
7, 31
30
29
45
20
24
IN1
IN2
IN3
IN4
VMON1
11
VMON2
11
VMON3
VMON4
VMON5
11
11
11
Name
Pin Type
Digital Input
Digital Input
Digital Input
Digital Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Ground
Ground
Power
Power
Power
Power
Voltage Range
VCCINP
VCCINP
1, 2
1, 3
Description
PLD Logic Input 1 Registered by MCLK
PLD Logic Input 2 Registered by MCLK
PLD Logic Input 3 Registered by MCLK
PLD Logic Input 4 Registered by MCLK
Voltage Monitor 1 Input
Voltage Monitor 2 Input
Voltage Monitor 3 Input
Voltage Monitor 4 Input
Voltage Monitor 5 Input
Voltage Monitor 6 Input
Voltage Monitor 7 Input
Voltage Monitor 8 Input
Voltage Monitor 9 Input
Voltage Monitor 10 Input
Digital Ground
Analog Ground
Core VCC, Main Power Supply
Analog Power Supply
VCC for IN[1:4] Inputs
VCC for JTAG Logic Interface Pins
Alternate E
2
Programming Supply; use only when
the Device is
Not
Powered by V
CCD
and V
CCA
.
Open-Drain Output 1
VCCINP
1, 3
VCCINP
1, 3
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
-0.3V to 5.87V
Ground
Ground
2.8V to 3.96V
2.8V to 3.96V
2.25V to 5.5V
2.25V to 3.6V
VMON6
11
VMON7
11
VMON8
11
VMON9
11
VMON10
11
GNDD
GNDA
4
4
41, 23 VCCD
5
VCCA
5
VCCINP
VCCJ
APS
9
Alternate Programming
3.0V to 3.6V
Supply
Open Drain Output
6
0V to 13V
15
HVOUT1
Current Source/Sink
Open Drain Output
6
12.5µA to 100µA Source
High-voltage FET Gate Driver 1
100µA to 3000µA Sink
0V to 13V
Open-Drain Output 2
12.5µA to 100µA Source
High-voltage FET Gate Driver 2
100µA to 3000µA Sink
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 3.96V
Open-Drain Output 3, (SMBUS Alert Active Low,
ispPAC-POWR1014A only).
Open-Drain Output 4
Open-Drain Output 5
Open-Drain Output 6
Open-Drain Output 7
Open-Drain Output 8
Open-Drain Output 9
Open-Drain Output 10
Open-Drain Output 11
Open-Drain Output 12
Open-Drain Output 13
Open-Drain Output 14
Device Reset (Active Low)
Pin internally pulled up.
14
HVOUT2
Current Source/Sink
Open Drain Output
6
Open Drain Output
6
Open Drain Output
Open Drain Output
Open Drain Output
6
6
6
13
12
11
10
9
8
6
5
4
3
2
1
40
SMBA_OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
RESETb
7
Open Drain Output
6
Open Drain Output
6
Open Drain Output
6
Open Drain Output
6
Open Drain Output
Open Drain Output
Open Drain Output
Digital I/O
6
6
6
3
ispPAC-POWR1014/A Data Sheet
Pin Descriptions (Cont.)
Number
42
43
21
22
16
18
17
19
39
38
Name
PLDCLK
MCLK
TDO
TCK
TMS
TDI
ATDI
TDISEL
SCL
8, 10
SDA
8, 10
Pin Type
Digital Output
Digital I/O
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Digital I/O
Voltage Range
0V to 3.96V
0V to 3.96V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
Description
250kHz PLD Clock Output (Tristate), CMOS
Output
Pin internally pulled up.
8MHz Clock I/O (Tristate), CMOS Drive.
Pin internally pulled up.
JTAG Test Data Out
JTAG Test Clock Input
JTAG Test Mode Select
Pin internally pulled up.
JTAG Test Data In, TDISEL pin = 1.Pin internally
pulled up.
JTAG Test Data In (Alternate), TDISEL Pin =
0.Pin internally pulled up.
Select TDI/ATDI Input
Pin internally pulled up.
I
2
C Serial Clock Input (ispPAC-POWR1014A
Only)
I
2
C Serial Data, Bi-directional Pin, Open Drain
(ispPAC-POWR1014A Only)
1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied
to GNDD.
2. IN1 pin can also be controlled through JTAG interface.
3. [IN2..IN4] can also be controlled through I
2
C/SMBus interface (ispPAC-POWR1014A only).
4. GNDA and GNDD pins must be connected together on the circuit board.
5. VCCD and VCCA pins must be connected together on the circuit board.
6. Open-drain outputs require an external pull-up resistor to a supply.
7. The RESETb pin should only be used for cascading two or more ispPAC-POWR1014/A devices.
8. These pins should be connected to GNDD (ispPAC-POWR1014 only).
9. The APS pin MUST be left floating when V
CCD
and V
CCA
are powered.
10. SCL should be tied high and SDA is don’t care when I
2
C registers are accessed through the JTAG interface (ispPAC-POWR1014A only).
11. The VMON inputs can be biased independently from VCC. Unused VMON inputs should be tied to GND.
4
ispPAC-POWR1014/A Data Sheet
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent dam-
age to the device. Functional operation of the device at these or any other conditions beyond those indicated in the
recommended operating conditions of this specification is not implied.
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