DS26521
Single T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26521 is a single-channel framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
FEATURES
Complete T1, E1, or J1 Long-Haul/Short-Haul
Transceiver (LIU plus Framer)
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26521
T1/E1/J1
NETWORK
T1/J1/E1
Transceiver
BACKPLANE
TDM
ORDERING INFORMATION
PART
DS26521LN
DS26521LN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
64 LQFP
64 LQFP
Controlled by 8-Bit Parallel Port Interface or
Serial Peripheral Interface (SPI)
Features Continued in Section
2.
+ Denotes lead-free/RoHS compliant device.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1 of 258
REV: 111606
DS26521 Single T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
1.1
DETAILED DESCRIPTION ...............................................................................................9
M
AJOR
O
PERATING
M
ODES
.............................................................................................................9
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
FEATURE HIGHLIGHTS ................................................................................................10
G
ENERAL
......................................................................................................................................10
L
INE
I
NTERFACE
............................................................................................................................10
C
LOCK
S
YNTHESIZER
....................................................................................................................10
J
ITTER
A
TTENUATOR
.....................................................................................................................10
F
RAMER
/F
ORMATTER
....................................................................................................................10
S
YSTEM
I
NTERFACE
......................................................................................................................11
HDLC C
ONTROLLERS
...................................................................................................................12
T
EST AND
D
IAGNOSTICS
................................................................................................................12
M
ICROCONTROLLER
P
ARALLEL
P
ORT
.............................................................................................12
S
LAVE
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) F
EATURES
............................................................12
3.
4.
5.
6.
7.
7.1
APPLICATIONS..............................................................................................................13
SPECIFICATIONS COMPLIANCE .................................................................................14
ACRONYMS AND GLOSSARY......................................................................................16
BLOCK DIAGRAMS .......................................................................................................17
PIN DESCRIPTIONS ......................................................................................................19
P
IN
F
UNCTIONAL
D
ESCRIPTION
......................................................................................................19
8.
8.1
FUNCTIONAL DESCRIPTION........................................................................................25
M
ICROPROCESSOR
I
NTERFACE
......................................................................................................25
Parallel Port Mode................................................................................................................................ 25
SPI Serial Port Mode............................................................................................................................ 25
SPI Functional Timing Diagrams ......................................................................................................... 25
Backplane Clock Generation ............................................................................................................... 28
8.1.1
8.1.2
8.1.3
8.2
8.3
8.4
8.5
8.6
8.7
8.8
C
LOCK
S
TRUCTURE
.......................................................................................................................28
R
ESETS AND
P
OWER
-D
OWN
M
ODES
..............................................................................................29
I
NITIALIZATION AND
C
ONFIGURATION
..............................................................................................30
Example Device Initialization Sequence .............................................................................................. 30
8.2.1
8.4.1
G
LOBAL
R
ESOURCES
....................................................................................................................30
P
ORT
R
ESOURCES
........................................................................................................................30
D
EVICE
I
NTERRUPTS
.....................................................................................................................30
S
YSTEM
B
ACKPLANE
I
NTERFACE
...................................................................................................32
Elastic Stores ....................................................................................................................................... 32
IBO Multiplexer..................................................................................................................................... 35
H.100 (CT Bus) Compatibility .............................................................................................................. 36
Receive and Transmit Channel Blocking Registers............................................................................. 37
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 37
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 37
T1 Framing........................................................................................................................................... 38
E1 Framing........................................................................................................................................... 41
T1 Transmit Synchronizer .................................................................................................................... 43
Signaling .............................................................................................................................................. 44
T1 Data Link......................................................................................................................................... 48
E1 Data Link......................................................................................................................................... 50
Maintenance and Alarms ..................................................................................................................... 51
2 of 258
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
F
RAMERS
......................................................................................................................................38
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
DS26521 Single T1/E1/J1 Transceiver
8.9.8
8.9.9
8.9.10
8.9.11
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
E1 Automatic Alarm Generation .......................................................................................................... 54
Error-Count Registers .......................................................................................................................... 55
DS0 Monitoring Function...................................................................................................................... 57
Transmit Per-Channel Idle Code Insertion........................................................................................... 58
Receive Per-Channel Idle Code Insertion............................................................................................ 58
Per-Channel Loopback ........................................................................................................................ 58
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 58
T1 Programmable In-Band Loop Code Generator............................................................................... 59
T1 Programmable In-Band Loop Code Detection................................................................................ 60
Framer Payload Loopbacks ................................................................................................................. 61
8.10
8.10.1
8.10.2
HDLC C
ONTROLLERS
................................................................................................................62
Receive HDLC Controller..................................................................................................................... 62
Transmit HDLC Controller.................................................................................................................... 65
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................67
LIU Operation....................................................................................................................................... 69
Transmitter ........................................................................................................................................... 70
Receiver ............................................................................................................................................... 73
Jitter Attenuator.................................................................................................................................... 76
LIU Loopbacks ..................................................................................................................................... 77
8.12
8.12.1
8.12.2
B
IT
-E
RROR
-R
ATE
T
EST
(BERT) F
UNCTION
................................................................................79
BERT Repetitive Pattern Set ............................................................................................................... 80
BERT Error Counter............................................................................................................................. 80
9.
9.1
DEVICE REGISTERS .....................................................................................................81
R
EGISTER
L
ISTINGS
......................................................................................................................81
Global Register List.............................................................................................................................. 82
Framer Register List............................................................................................................................. 83
LIU and BERT Register List................................................................................................................. 90
Global Register Bit Map ....................................................................................................................... 91
Framer Register Bit Map ...................................................................................................................... 92
LIU Register Bit Map .......................................................................................................................... 100
BERT Register Bit Map ...................................................................................................................... 100
9.1.1
9.1.2
9.1.3
9.2
R
EGISTER
B
IT
M
APS
......................................................................................................................91
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.5
9.6
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................101
F
RAMER
R
EGISTER
D
EFINITIONS
.................................................................................................109
Receive Register Definitions.............................................................................................................. 109
Transmit Register Definitions............................................................................................................. 168
9.4.1
9.4.2
LIU R
EGISTER
D
EFINITIONS
.........................................................................................................203
BERT R
EGISTER
D
EFINITIONS
.....................................................................................................212
10.
10.1
10.2
10.3
10.4
FUNCTIONAL TIMING .................................................................................................220
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................220
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................225
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................230
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................232
11.
11.1
11.2
OPERATING PARAMETERS .......................................................................................235
T
HERMAL
C
HARACTERISTICS
....................................................................................................236
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................236
12.
12.1
AC TIMING CHARACTERISTICS ................................................................................237
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................237
Parallel Port Mode.............................................................................................................................. 237
SPI Bus Mode .................................................................................................................................... 240
12.1.1
12.1.2
12.2
12.3
JTAG I
NTERFACE
T
IMING
.........................................................................................................248
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................249
3 of 258
DS26521 Single T1/E1/J1 Transceiver
13.
13.1
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ..............................................250
TAP C
ONTROLLER
S
TATE
M
ACHINE
.........................................................................................251
Test-Logic-Reset................................................................................................................................ 251
Run-Test-Idle ..................................................................................................................................... 251
Select-DR-Scan ................................................................................................................................. 251
Capture-DR ........................................................................................................................................ 251
Shift-DR.............................................................................................................................................. 251
Exit1-DR............................................................................................................................................. 251
Pause-DR........................................................................................................................................... 251
Exit2-DR............................................................................................................................................. 251
Update-DR ......................................................................................................................................... 251
Select-IR-Scan ............................................................................................................................... 251
Capture-IR ...................................................................................................................................... 252
Shift-IR............................................................................................................................................ 252
Exit1-IR........................................................................................................................................... 252
Pause-IR......................................................................................................................................... 252
Exit2-IR........................................................................................................................................... 252
Update-IR ....................................................................................................................................... 252
SAMPLE:PRELOAD .......................................................................................................................... 254
BYPASS ............................................................................................................................................. 254
EXTEST ............................................................................................................................................. 254
CLAMP............................................................................................................................................... 254
HIGHZ ................................................................................................................................................ 254
IDCODE ............................................................................................................................................. 254
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.1.10
13.1.11
13.1.12
13.1.13
13.1.14
13.1.15
13.1.16
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
I
NSTRUCTION
R
EGISTER
...........................................................................................................254
13.3
13.4
13.4.1
13.4.2
13.4.3
JTAG ID C
ODES
......................................................................................................................255
T
EST
R
EGISTERS
.....................................................................................................................255
Boundary Scan Register .................................................................................................................... 255
Bypass Register ................................................................................................................................. 255
Identification Register......................................................................................................................... 255
14.
15.
15.1
PIN CONFIGURATION .................................................................................................256
PACKAGE INFORMATION ..........................................................................................257
64-P
IN
LQFP (56-G4019-001) ................................................................................................257
16.
DOCUMENT REVISION HISTORY...............................................................................258
4 of 258
DS26521 Single T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0).............................................. 26
Figure 8-2. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 0).............................................. 26
Figure 8-3. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 1).............................................. 26
Figure 8-4. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, SPI_CPHA = 1).............................................. 26
Figure 8-5. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 0) .............................................. 27
Figure 8-6. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 0) .............................................. 27
Figure 8-7. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 1) .............................................. 27
Figure 8-8. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 1) .............................................. 27
Figure 8-9. Backplane Clock Generation................................................................................................................... 28
Figure 8-10. Device Interrupt Information Flow Diagram........................................................................................... 31
Figure 8-11. IBO Example Circuit .............................................................................................................................. 35
Figure 8-12. RSYNC Input in H.100 (CT Bus) Mode................................................................................................. 36
Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ..................................................................... 37
Figure 8-14. CRC-4 Recalculate Method .................................................................................................................. 58
Figure 8-15. Receive HDLC Example........................................................................................................................ 64
Figure 8-16. HDLC Message Transmit Example....................................................................................................... 66
Figure 8-17. Basic Balanced Network Connections .................................................................................................. 68
Figure 8-18. T1/J1 Transmit Pulse Templates .......................................................................................................... 71
Figure 8-19. E1 Transmit Pulse Templates ............................................................................................................... 72
Figure 8-20. Typical Monitor Application ................................................................................................................... 74
Figure 8-21. Jitter Attenuation ................................................................................................................................... 76
Figure 8-22. Analog Loopback................................................................................................................................... 77
Figure 8-23. Local Loopback ..................................................................................................................................... 77
Figure 8-24. Remote Loopback ................................................................................................................................. 78
Figure 8-25. Dual Loopback ...................................................................................................................................... 78
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 220
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 220
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 221
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 221
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 222
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 223
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 224
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 225
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 225
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 226
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 226
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 227
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 228
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 229
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 230
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 230
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 231
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 231
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 232
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 232
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 233
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 233
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 234
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 238
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 238
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 239
Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 239
Figure 12-5. SPI Interface Timing Diagram ............................................................................................................. 241
Figure 12-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 243
5 of 258
51mcu
京公网安备 11010802033920号
EEWORLD
