fpga - field programmable gate array cpld - apex II 2432 macro 492 ios
| Parameter Name | Attribute value |
| Is it lead-free? | Contains lead |
| Is it Rohs certified? | incompatible |
| Maker | Altera (Intel) |
| Parts packaging code | BGA |
| package instruction | 27 X 27 MM, 1 MM PITCH, FINE LINE, BGA-672 |
| Contacts | 672 |
| Reach Compliance Code | _compli |
| ECCN code | 3A001.A.7.A |
| JESD-30 code | S-PBGA-B672 |
| JESD-609 code | e0 |
| length | 27 mm |
| Humidity sensitivity level | 3 |
| Number of I/O lines | 492 |
| Number of entries | 480 |
| Number of logical units | 24320 |
| Output times | 480 |
| Number of terminals | 672 |
| Maximum operating temperature | 85 °C |
| Minimum operating temperature | |
| organize | 492 I/O |
| Output function | MACROCELL |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | BGA |
| Encapsulate equivalent code | BGA672,26X26,40 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| Peak Reflow Temperature (Celsius) | 220 |
| power supply | 1.5,1.5/3.3 V |
| Programmable logic type | LOADABLE PLD |
| propagation delay | 1.94 ns |
| Certification status | Not Qualified |
| Maximum seat height | 2.1 mm |
| Maximum supply voltage | 1.575 V |
| Minimum supply voltage | 1.425 V |
| Nominal supply voltage | 1.5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | OTHER |
| Terminal surface | Tin/Lead (Sn63Pb37) |
| Terminal form | BALL |
| Terminal pitch | 1 mm |
| Terminal location | BOTTOM |
| Maximum time at peak reflow temperature | 30 |
| width | 27 mm |
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