LVPECL, LVDS Crystal Oscillator Data Sheet
Previous Vectron Model VCC6
VC-707
VC-707
Description
Vectron’s VC-707 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off 3.3 volt supply, hermetically
sealed 5x7 ceramic package.
Features
•
•
•
•
•
•
3.3V Operation
Output Frequencies to 800MHz
Differential Output
Enable/Disable
-10/70°C or -40/85°C Operation
Hermetically Sealed 5x7 Ceramic Package
•
•
•
•
•
•
•
•
•
Applications
Storage Area Networking
Telecom
Ethernet, GE, SynchE
Fiber Channel
PON
Driving A/D’s, D/A’s, FPGA’s
Test and Measurement
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
Crystal
Oscillator
PLL
E/D or NC
E/D or NC
Gnd
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page1
Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
2
Stability
2,3
(Ordering Options)
Outputs
Output Logic Levels
4
, -10/70°C
Output Logic High
Output Logic Low
Output Logic Levels
4
, -40/85°C
Output Logic High
Output Logic Low
Output Rise and Fall Time
4
Rise Time
Fall Time
Output Load
Duty Cycle
5
Jitter (12 kHz - 20 MHz BW)155.52MHz
6
Period Jitter
7
RMS
P/P
Output Enabled
8
Output Disabled
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
t
SU
T
OP
-10/70 or -40/85
фJ
фJ
45
V
OH
V
OL
V
OH
V
OL
t
R
/t
F
V
DD
-1.025
V
DD
-1.810
V
DD
-1.085
V
DD
-1.830
V
DD
-0.880
V
DD
-1.620
V
DD
-0.880
V
DD
-1.555
600
600
50 ohms to V
DD
-1.3V
50
2
4
30
Enable/Disable
V
IH
V
IL
0.7*V
DD
0.3*V
DD
±200
10
V
V
uA
ms
°C
55
%
ps
ps
ps
V
Symbol
V
DD
I
DD
Min
Supply
3.15
Frequency
Typical
3.3
Maximum
3.45
100
Units
V
mA
MHz
ppm
f
N
270
±20, ±25, ±32, ±50, ±100
800
V
ps
ps
Package Size
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2
mm
1. The VC-707 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations,, aging and IR reflow.
4. Figure 2 defines these parameters and Figure 1 defines the test circuit.
5. Duty Cycle is defines as the On/Time Period.
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VC-706 series”.
7. Measured using a LeCroy 8600, 25K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
V
DD
-1.3V
1
2
3
-1.3V
6
5
4
50
50
t
R
V
OH
50%
V
OL
On Time
Period
Figure 2
t
F
NC
NC
Figure 1
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Performance Specifications
Table 2. Electrical Performance, LVDS Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
2
Stability
2,3,
(Ordering Options)
Outputs
Output Logic Levels
4
Output Logic High
Output Logic Low
Differential Output
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current
Output Load
Output Rise and Fall Time
4
Rise Time
Fall Time
Duty Cycle
5
Jitter (12 kHz - 20 MHz BW)155.52MHz
6
Period Jitter
7
RMS
P/P
Output Enabled
8
Output Disabled
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2
фJ
фJ
t
R
/t
F
100 ohms differential
600
600
45
50
2
4
30
Enable/Disable
V
IH
V
IL
0.7*V
DD
0.3*V
DD
±200
10
V
V
uA
ms
°C
mm
55
ps
ps
%
ps
ps
ps
1.125
1.25
V
OH
V
OL
1.40
1.10
330
1.6
454
50
1.375
50
10
V
Symbol
V
DD
I
DD
Min
Supply
3.15
Frequency
Typical
3.3
Maximum
3.45
60
Units
V
mA
MHz
ppm
f
N
260
800.000
±20, ±25, ±32, ±50, ±100
0.9
247
mV
mV
V
mV
uA
1. The VC-707 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations,, aging and IR reflow.
4. Figure 2 defines these parameters and Figure 3 defines the test circuit.
5. Duty Cycle is defines as the On/Time Period.
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series”.
7. Measured using a LeCroy 8600, 25K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
Out
50
50
0.01 uF
DC
Out
6
1
5
2
4
3
Figure 3
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Package and Pinout
Table 3. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
E/D or NC
GND
f
O
Cf
O
V
DD
Function
Enable Disable or No Connection
Enable Disable or No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
The Enable/Disable function is set at the factory on either pin 1
or pin 2 and is an ordering option
6
7.0±0.15
5
Part Number
Frequency
Date Code
4
6
7.49±0.15
5
Part Number
Frequency
Date Code
4
5.0±0.15
5.08±0.15
1
2
1.397
3
1.6 max
1.27
1
2
1.397
3
2.16 max
1.27
1
6
2
Bottom View
5
3
3.57
4
1
6
2
Bottom View
5
3
3.57
4
2.54
5.08
5.08
2.54
Figure 4 Package A Outline Drawing
Figure 5 Optional Package Outline Drawing
The VC-707 can be supplied in one of two package options and
Figure 4 shows the primary package used. The pad layout and
dimesnions are identical and a reel would include only 1 of the
two options
1.78
1.96
3.66
2.54
5.08
Figure 6 Pad Layout
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
LVPECL Application Diagrams
Figure 7 Standard PECL Output Configuration
Figure 8 Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms
for 3.3V operation.
Resistor values are typically 82 to 120 ohms
for 2.5V operation.
Figure 9 Pull-Up Pull Down Termination
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62
ohms and the resistor to supply is 240 ohms
The VC-707 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes
on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme
as shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
LVDS Application Diagrams
V
CC
LVDS
Driver
OUT+
OUT-
100
LVDS
Receiver
LVDS
Driver
100
Receiver
Figure 11 LVDS to LVDS Connection, Internal 100ohm
Some LVDS structures have an internal 100 ohm resistor
on the input and do not need additional components.
Figure 10 Standard LVDS
Output Configuration
Figure 12 LVDS to LVDS Connection
External 100ohm and AC blocking caps
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Environmental and IR Compliance
Table 4. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Fine and Gross Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Condition
MIL-STD-883 Method 2002
MIL-STD-883 Method 2007
MIL-STD-883 Method 1010
MIL-STD-883 Method 2003
MIL-STD-883 Method 1014
MIL-STD-883 Method 2015
MSL1
Gold over Nickel
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
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