18-Mbit QDR II SRAM
Four-Word Burst Architecture
18-Mbit QDR
®
II SRAM Four-Word Burst Architecture
CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
®
Features
■
Configurations
CY7C1311KV18 – 2 M × 8
CY7C1911KV18 – 2 M × 9
CY7C1313KV18 – 1 M × 18
CY7C1315KV18 – 512 K × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
333-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
®
II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in ×8, ×9, ×18, and ×36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V (±0.1 V); I/O V
DDQ
= 1.4 V to V
DD
❐
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
PLL for accurate data placement
■
■
■
■
Functional Description
The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and
CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with QDR II architecture. QDR II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR II architecture has
separate data inputs and data outputs to completely eliminate
the need to ‘turnaround’ the data bus that exists with common
I/O devices. Each port can be accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II read and write ports are independent of one
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
associated with four 8-bit words (CY7C1311KV18), 9-bit words
(CY7C1911KV18), 18-bit words (CY7C1313KV18), or 36-bit
words (CY7C1315KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
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Selection Guide
Description
Maximum operating frequency
Maximum operating current
×8
×9
× 18
× 36
333 MHz
333
520
520
530
730
300 MHz
300
490
490
500
670
250 MHz
250
430
430
440
590
200 MHz
200
380
380
390
500
167 MHz
167
340
340
350
450
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-58904 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 1, 2011
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CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
Logic Block Diagram (CY7C1311KV18)
D
[7:0]
8
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512 K x 8 Array
512 K x 8 Array
512 K x 8 Array
512 K x 8 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
32
V
REF
WPS
NWS
[1:0]
16
Control
Logic
16
Reg.
Reg.
Reg. 8
8
8
8
CQ
8
Q
[7:0]
Logic Block Diagram (CY7C1911KV18)
D
[8:0]
9
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512 K x 9 Array
512 K x 9 Array
512 K x 9 Array
512 K x 9 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
36
V
REF
WPS
BWS
[0]
18
Control
Logic
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q
[8:0]
Document Number: 001-58904 Rev. *C
Page 2 of 33
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CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
Logic Block Diagram (CY7C1313KV18)
D
[17:0]
18
Read Add. Decode
Write Add. Decode
A
(17:0)
18
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
18
A
(17:0)
256 K x 18 Array
256 K x 18 Array
256 K x 18 Array
256 K x 18 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
72
V
REF
WPS
BWS
[1:0]
36
Control
Logic
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1315KV18)
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(16:0)
17
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
17
A
(16:0)
128 K x 36 Array
128 K x 36 Array
128 K x 36 Array
128 K x 36 Array
K
K
CLK
Gen.
Control
Logic
RPS
C
C
CQ
DOFF
Read Data Reg.
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
Document Number: 001-58904 Rev. *C
Page 3 of 33
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CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
Contents
Pin Configuration ............................................................. 5
165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
Concurrent Transactions ........................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Application Example ...................................................... 11
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR II SRAM ........................... 21
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 24
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
Switching Characteristics .............................................. 26
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagram ............................................................ 30
Acronyms ....................................................................... 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Document Number: 001-58904 Rev. *C
Page 4 of 33
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CY7C1311KV18, CY7C1911KV18
CY7C1313KV18, CY7C1315KV18
Pin Configuration
The pin configurations for CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 follow.
[1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1311KV18 (2 M × 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1911KV18 (2 M × 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-58904 Rev. *C
Page 5 of 33
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